Revision 1.25 – December 18, 2006
440EP – PPC440EP Embedded Processor
Data Sheet
Table 2. DCR Address Map (4KB of Device Configuration Registers)
Function
Total DCR Address Space1
Start Address
End Address
Size
1KW (4KB)1
000
3FF
By function:
Reserved
000
00C
00E
010
012
014
016
018
020
030
040
070
080
090
0A0
0A8
0B0
0B8
0C0
0D0
0E0
100
140
180
200
210
300
340
00B
00D
00F
011
013
015
017
01F
02F
03F
06F
07F
08F
09F
0A7
0AF
0B7
0BF
0CF
0DF
0FF
13F
17F
1FF
20F
2FF
33F
3FF
12W
2W
Clocking Power On Reset (CPR)
System DCRs (SDR)
Memory Controller (SDRAM)
External Bus Controller (EBC)
Reserved
2W
2W
2W
2W
PLB 128 Performance Monitor (PPM)
Reserved
2W
8W
PLB 128 to PLB 64 Bridge Out
PLB 64 to PLB 128 Bridge In
Reserved
16W
16W
64W
16W
16W
16W
8W
PLB 64 Arbiter
PLB 128 Arbiter
PLB 64 to OPB Bridge Out
Reserved
OPB to PLB 64 Bridge In
Power Management
Reserved
8W
8W
8W
Interrupt Controller 0
Interrupt Controller 1
Reserved
16W
16W
32W
64W
64W
128W
16W
512W
64W
512W
DMA to PLB 64 Controller
Reserved
Ethernet MAL
PLB 128 to OPB Bridge
Reserved
DMA to PLB 128 Controller
Reserved
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit
(word) register. One kiloword (1024W) equals 4KB (4096 B).
AMCC Proprietary
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
