Revision 1.25 – December 18, 2006
440EP – PPC440EP Embedded Processor
Data Sheet
Block Diagram
Figure 2. PPC440EP Functional Block Diagram
10
Clock
Control
Reset
External
Power
Mgmt
Interrupts
66MHz max
- 32 bits
- 6 devices
66MHz max
- 30-bit addr
- 16-bit data
DCRs
Timers
MMU
UIC
PPC440
Processor Core
DCR Bus
FPU
External
NAND
Flash
Controller
PCI
Bridge
Trace
JTAG
Peripheral
Controller
32KB
I-Cache
32KB
D-Cache
Performance
Monitor
PLB
Bridge
PLB (PLB4—128 bits)
PLB (PLB3—64 bits)
GPT
OPB
DMA
Controller
DMA
OPB
Bridge
Bridge
Controller
DDR SDRAM
Controller
On-chip Peripheral Bus (OPB 0)
OPB 1
USB 2.0
Device
USB 1.1
Host
Ethernet
10/100
x2
IIC
x2
UART
x4
SPI
GPIO
BSC
266MHz max
- 13-bit addr
- 32-bit data
MAL
1 MII
1.1PHY 1.1PHY
UTMI
ZMII
or
2 RMII
or
2 SMII
D+/D−
D+/D−
™
The PPC440EP is a system on a chip (SOC) using IBM CoreConnect Bus Architecture.
6
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
