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PPC440EP-3JC533C 参数 Datasheet PDF下载

PPC440EP-3JC533C图片预览
型号: PPC440EP-3JC533C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA456, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, BGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 87 页 / 1210 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.29 – May 07, 2008  
440EP – PPC440EP Embedded Processor  
Data Sheet  
Example 2:  
In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If ECC  
is enabled, Stage 3 data must be sampled (see Example 3). In this example, T and T are system dependent  
T
TE  
and taken into account by controller initialization software.  
Figure 13. DDR SDRAM Read Cycle Timing—Example 2  
DQS at pin  
Data at pin  
D0  
D1  
D3  
D2  
T
SIN  
DQS Stage 1 C  
Data in Stage 1 D  
D0  
D1  
D3  
D2  
T
DIN  
T
P
High  
Low  
D0  
D1  
D2  
D3  
Data out Stage 1  
D0  
D2  
PLB Clock  
Read Clock Delayed  
T
P
D0  
D1  
High  
D2  
D3  
Data out Stage 2  
Low  
High  
Low  
D2  
D3  
D0  
D1  
Data in at RDSP  
without ECC  
T
T
T
TE  
High  
Low  
D0  
D1  
D2  
D3  
Data in at RDSP  
with ECC  
High  
Low  
D0  
D1  
D2  
D3  
Data out at RDSP  
without ECC  
(2)  
T = Propagation delay from Stage 2 input to RDSP input w/o ECC  
T
T
= Propagation delay from Stage 2 input to RDSP input with ECC  
TE  
82  
AMCC Proprietary  
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