440EP – PPC440EP Embedded Processor
Revision 1.26 – April 25, 2007
Data Sheet
Table 1. System Memory Address Map (Sheet 2 of 2)
Function
Reserved
General Purpose Timer
Reserved
UART0
Reserved
UART1
Reserved
UART2
Reserved
UART3
Reserved
IIC0
Reserved
IIC1
Internal Peripherals
Reserved
SPI
Reserved
OPB Arbiter (OPB 0)
Reserved
GPIO0 Controller
Reserved
GPIO1 Controller
Reserved
Ethernet PHY ZMII
Reserved
Ethernet 0 Controller
Ethernet 1 Controller
USB 1.1 Host
Reserved
EBC
Boot space (EBC Bank 0 and PCI)
Notes:
1. DDR SDRAM can be located anywhere in the Local Memory area of the memory map.
2. EBC and PCI are relocatable, but this map reflects the suggested configuration.
Sub Function
Start Address
0 EF50 0000
0 EF60 0000
0 EF60 0100
0 EF60 0300
0 EF60 0308
0 EF60 0400
0 EF60 0408
0 EF60 0500
0 EF60 0508
0 EF60 0600
0 EF60 0608
0 EF60 0700
0 EF60 0720
0 EF60 0800
0 EF60 0820
0 EF60 0900
0 EF60 0907
0 EF60 0A00
0 EF60 0A40
0 EF60 0B00
0 EF60 0B80
0 EF60 0C00
0 EF60 0C80
0 EF60 0D00
0 EF60 0D10
0 EF60 0E00
0 EF60 0F00
0 EF60 1000
0 EF60 1080
0 F000 0000
0 FFE0 0000
End Address
0 EF5F FFFF
0 EF60 00FF
0 EF60 02FF
0 EF60 0307
0 EF60 03FF
0 EF60 0407
0 EF60 04FF
0 EF60 0507
0 EF60 05FF
0 EF60 0607
0 EF60 06FF
0 EF60 071F
0 EF60 07FF
0 EF60 081F
0 EF60 08FF
0 EF60 0906
0 EF60 09FF
0 EF60 0A3F
0 EF60 0AFF
0 EF60 0B7F
0 EF60 0BFF
0 EF60 0C7F
0 EF60 0CFF
0 EF60 0D0F
0 EF60 0DFF
0 EF60 0EFF
0 EF60 0FFF
0 EF60 107F
0 EFFF FFFF
0 FFDF FFFF
0 FFFF FFFF
254MB
2MB
256B
256B
128B
16B
128B
128B
64B
6B
32B
32B
8B
8B
8B
8B
256B
Size
AMCC Proprietary
7
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
