440EP – PPC440EP Embedded Processor
Revision 1.26 – April 25, 2007
Data Sheet
Block Diagram
Figure 2. PPC440EP Functional Block Diagram
10
External
Interrupts
Clock
Control
Reset
Timers
MMU
UIC
Power
Mgmt
DCRs
66MHz max
- 30-bit addr
- 16-bit data
66MHz max
- 32 bits
- 6 devices
PPC440
Processor Core
FPU
JTAG
32KB
D-Cache
Performance
Monitor
PLB (PLB4—128 bits)
Trace
32KB
I-Cache
DCR Bus
External
Peripheral
Controller
NAND
Flash
Controller
PCI
Bridge
PLB
Bridge
OPB
Bridge
PLB (PLB3—64 bits)
DMA
Controller
DDR SDRAM
Controller
OPB
Bridge
DMA
Controller
GPT
OPB 1
On-chip Peripheral Bus (OPB 0)
266MHz max
- 13-bit addr
- 32-bit data
USB 2.0
Device
UTMI 1.1PHY
USB 1.1
Host
1.1PHY
GPIO
SPI
IIC
x2
BSC
UART
x4
Ethernet
10/100
x2
ZMII
MAL
1 MII
or
2 RMII
or
2 SMII
D+/D−
D+/D−
The PPC440EP is a system on a chip (SOC) using IBM CoreConnect Bus
™
Architecture.
AMCC Proprietary
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
