Revision 1.26 – April 25, 2007
440EP – PPC440EP Embedded Processor
Data Sheet
Table 8. Recommended DC Operating Conditions (Sheet 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Input Logic High (2.5V SSTL)
Symbol
Minimum
Typical
Maximum
Unit
V
Notes
SVREF+0.18
SVDD+0.3
Input Logic High (2.5V CMOS, 3.3V tolerant receiver)
Input Logic High (3.3V PCI)
1.7
V
VIH
0.5OVDD
OVDD+0.5
V
1
Input Logic High (3.3V LVTTL)
+2.0
-0.3
+3.6
V
SVREF-0.18
Input Logic Low (2.5V SSTL)
V
Input Logic Low (2.5V CMOS, 3.3V tolerant receiver)
Input Logic Low (3.3V PCI)
0.7
V
VIL
VOH
VOL
0.35OVDD
-0.5
0
V
1
Input Logic Low (3.3V LVTTL)
+0.8
V
SVDD
Output Logic High (2.5V SSTL)
+1.95
2.0
V
SVDD
OVDD
OVDD
Output Logic High (2.5V CMOS, 3.3V tolerant receiver)
Output Logic High (3.3V PCI)
V
0.9OVDD
V
1
1
Output Logic High (3.3V LVTTL)
+2.4
0
V
V
V
V
V
Output Logic Low (2.5V SSTL)
0.55
0.4
Output Logic Low (2.5V CMOS, 3.3V tolerant receiver)
Output Logic Low (3.3V PCI)
0.1OVDD
Output Logic Low (3.3V LVTTL)
0
0
+0.4
0
IIL1
IIL2
Input Leakage Current (No pull-up or pull-down)
μA
μA
μA
V
Input Leakage Current for Pull-Down
0 (LPDL)
-150 (LPDL)
200 (MPUL)
0 (MPUL)
+3.9
IIL3
Input Leakage Current for Pull-Up
VIMAO
VIMAU
VOMAO
VOMAU3
Input Max Allowable Overshoot (3.3V LVTTL)
Input Max Allowable Undershoot (3.3V LVTTL)
Output Max Allowable Overshoot (3.3V LVTTL)
Output Max Allowable Undershoot (3.3V LVTTL)
-0.6
-0.6
V
+3.9
V
V
Case Temperature:
333MHz, 400MHz, and 533MHz parts in any package
667MHz parts in the E-PBGA package
667MHz parts in the TE-PBGA package.
-40
-40
-40
+100
+85
+95
TC
°C
Notes:
1. PCI drivers meet PCI specifications.
2. SVREF = SVDD/2
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440EP. See “Absolute Maximum Ratings” on page 59.
60
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
