Revision 1.26 – April 25, 2007
440EP – PPC440EP Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 1 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
PCI Interface
Description
I/O
Type
Notes
PCIAD00:31
PCIC0:3/BE0:3
PCIClk
Address/Data bus (bidirectional).
I/O
I/O
I
3.3V PCI
3.3V PCI
3.3V PCI
PCI Command/Byte Enables.
Provides timing to the PCI interface for PCI transactions.
Indicates the driving device has decoded its address as the
target of the current access.
PCIDevSel
PCIFrame
I/O
I/O
3.3V PCI
3.3V PCI
Driven by the current master to indicate beginning and
duration of an access.
Indicates that the specified agent is granted access to the bus.
When the internal arbiter is enabled, output is PCIGnt0. When
the internal arbiter is disabled, output is Req.
PCIGnt0/Req
PCIGnt1:5
O
O
3.3V PCI
3.3V PCI
Indicates that the specified agent is granted access to the bus.
Used only when internal PCI arbiter enabled.
Used as a chip select during configuration read and write
transactions.
PCIIDSel
PCIINT
I
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Level sensitive PCI interrupt.
O
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
PCIIRDY
PCIPar
I/O
I/O
I/O
Even parity.
Reports data parity errors during all PCI transactions except a
Special Cycle.
PCIPErr
Indicates to the PCI arbiter that the specified agent wishes to
use the bus. When the internal arbiter is enabled, input is
PCIReq0. When internal arbiter is disabled, input is Gnt.
PCIReq0/Gnt
I
3.3V PCI
An indication to the PCI arbiter that the specified agent wishes
to use the bus. Used only when internal PCI arbiter enabled.
PCIReq1:5
PCIReset
PCISErr
I
3.3V PCI
3.3V PCI
3.3V PCI
Brings PCI device registers and logic to a consistent state.
O
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
I/O
Current target is requesting the master to stop the current
transaction.
PCIStop
I/O
I/O
3.3V PCI
3.3V PCI
Target agent’s ability to complete the current data phase of the
transaction.
PCITRDY
50
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
