欢迎访问ic37.com |
会员登录 免费注册
发布采购

PPC405EZ-CSAFFFTX 参数 Datasheet PDF下载

PPC405EZ-CSAFFFTX图片预览
型号: PPC405EZ-CSAFFFTX
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerPC 405EZ嵌入式处理器 [PowerPC 405EZ Embedded Processor]
分类和应用: PC
文件页数/大小: 54 页 / 814 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号PPC405EZ-CSAFFFTX的Datasheet PDF文件第8页浏览型号PPC405EZ-CSAFFFTX的Datasheet PDF文件第9页浏览型号PPC405EZ-CSAFFFTX的Datasheet PDF文件第10页浏览型号PPC405EZ-CSAFFFTX的Datasheet PDF文件第11页浏览型号PPC405EZ-CSAFFFTX的Datasheet PDF文件第13页浏览型号PPC405EZ-CSAFFFTX的Datasheet PDF文件第14页浏览型号PPC405EZ-CSAFFFTX的Datasheet PDF文件第15页浏览型号PPC405EZ-CSAFFFTX的Datasheet PDF文件第16页  
Revision 1.27 - August 22, 2007  
PPC405EZ – PowerPC 405EZ Embedded Processor  
Preliminary Data Sheet  
• Loopback controls for isolating communications link faults  
• Break, parity, overrun, framing error simulation  
• OPB interface with optional DMA support  
IIC Bus Interface  
2
®
The Inter-Integrated Circuit (IIC) interface provides a Philips I C compatible interface operating up to 400kHz  
either as a master, a slave, or both with a bootstrap controller (BSC) included. During chip reset, the bootstrap  
controller can read configuration data from an IIC compatible memory device (e.g., EEPROM). This data can be  
used to replace the default configuration settings provided by the chip.  
Features include:  
• One IIC channel  
2
• Compliant with Philips Semiconductors I C Specification, dated 1995  
• 100 kHz or 400 kHz operation  
• 8-bit data  
• 10- or 7-bit address  
• Slave Transmit and Receive  
• Master Transmit and Receive  
• Multiple bus masters supported  
• Programmable as master, slave, or master/slave  
• Boot parameters read from IIC attached memory with IIC bootstrap controller  
• 32-bit OPB slave interface  
Serial Peripheral Interface (SPI/SCP)  
The Serial Peripheral Interface (SPI) (also known as the Serial Communications Port or SCP) is a full-duplex,  
synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SPI is a  
master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.  
Features include:  
• One SPI/SCP channel, full duplex synchronous  
• SPI/SCP master  
• Up to 40 MHz  
• Programmable internal loopback capabilities  
• Multi-master protocol supported  
• Independent masking of all interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive  
FIFO full, receive FIFO underflow, receive FIFO overflow)  
• Dynamic control of serial bit rate of data transfer (serial-master mode only)  
• Data Item size for each data transfer under programmer control (4-to-16 bits)  
• Boot from SPI supported  
• 32-bit OPB slave interface  
12  
AMCC Proprietary