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PPC405EP-3LB333CZ 参数 Datasheet PDF下载

PPC405EP-3LB333CZ图片预览
型号: PPC405EP-3LB333CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 405EP的PowerPC嵌入式处理器 [PowerPC 405EP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 50 页 / 805 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – September 10, 2007  
PPC405EP – PowerPC 405EP Embedded Processor  
On-Chip Memory (OCM)  
Data Sheet  
The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the  
processor core.  
Features include:  
Low-latency access to critical instructions and data  
Performance identical to cache hits without misses  
Contents change only under program control  
PLB to PCI Interface  
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor  
and local memory. This interface is compliant with version 2.2 of the PCI Specification.  
Features include:  
internal pci bus arbiter for up to three external devices at PCI bus speeds up to 66MHz. Internal arbiter use  
is optional and can be disabled for systems which employ an external arbiter.  
PCI bus frequency up to 66MHz  
- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum  
32-bit PCI address/data bus  
Power Management:  
- PCI Bus Power Management v1.1 compliant  
Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI  
Buffering between PLB and PCI:  
- PCI target 64-byte write post buffer  
- PCI target 96-byte read prefetch buffer  
- PLB slave 32-byte write post buffer  
- PLB slave 64-byte read prefetch buffer  
Error tracking/status  
Supports PCI target side configuration  
Supports processor access to all PCI address spaces:  
- Single-beat PCI I/O reads and writes  
- PCI memory single-beat and prefetch-burst reads and single-beat writes  
- Single-beat PCI configuration reads and writes (type 0 and type 1)  
- PCI interrupt acknowledge  
- PCI special cycle  
Supports PCI target access to all PLB address spaces  
Supports PowerPC processor boot from PCI memory  
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