Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Figure 1. PPC405EP Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
OCM
SRAM
Power
Mgmt
Event
Counters
Timers
MMU
DOCM
IOCM
OCM
Control
DCRs
UART
x2
PPC405
Processor Core
GPIO
IIC
GPT
DCR Bus
Trace
ICU
JTAG
DCU
16KB
I-Cache
16KB
D-Cache
On-chip Peripheral Bus (OPB)
OPB
Arb
DMA
Ethernet
x2
Controller
(4-Channel)
MAL
Bridge
Arb
Processor Local Bus (PLB)
External
Bus
Controller
SDRAM
Controller
PCI Bridge
66 MHz max (async)
MII
13-bit addr
32-bit data
29-bit addr
16-bit data
TM
The PPC405EP is designed using the IBM Microelectronics Blue Logic methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
TM
way to create complex ASICs using IBM CoreConnect Bus Architecture.
AMCC
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
