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PPC405EP-3LB333CZ 参数 Datasheet PDF下载

PPC405EP-3LB333CZ图片预览
型号: PPC405EP-3LB333CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 405EP的PowerPC嵌入式处理器 [PowerPC 405EP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 50 页 / 805 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – September 10, 2007  
PPC405EP – PowerPC 405EP Embedded Processor  
Data Sheet  
c. TCMax = TJMax – P×θJC, where TJMax is maximum junction temperature and P is power consumption.  
Table 9. Recommended DC Operating Conditions (Sheet 1 of 2)  
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended  
conditions can affect device reliability.  
Notes:  
1. PCI drivers meet PCI specifications.  
2. See “5V-Tolerant Input Current” on page 38.  
Parameter  
Symbol  
Minimum  
+1.65  
+1.7  
Typical  
+1.8  
Maximum  
+1.95  
+1.9  
Unit  
V
Notes  
VDD  
Logic Supply Voltage (133, 200, 266MHz)  
Logic Supply Voltage (333MHz)  
I/O Supply Voltage  
VDD  
+1.8  
V
OVDD  
AVDD  
AVDD  
+3.0  
+3.3  
+3.6  
V
PLL Supply Voltage (133, 200, 266MHz)  
PLL Supply Voltage (333MHz)  
+1.65  
+1.7  
+1.8  
+1.95  
+1.9  
V
+1.8  
V
Input Logic High  
(1.8V CMOS receivers)  
VIH  
VIH  
VIH  
VIL  
0.65VDD  
0.5OVDD  
VDD  
V
V
Input Logic High  
(3.3V PCI receivers)  
OVDD+0.5  
Input Logic High  
(3.3V LVTTL, 5V tolerant receivers)  
+2.0  
+5.5  
V
Input Logic Low  
(1.8V CMOS receivers)  
0.65VDD  
0.35OVDD  
0
-0.5  
V
Input Logic Low  
(3.3V PCI receivers)  
VIL  
V
Input Logic Low  
(3.3V LVTTL, 5V tolerant receivers)  
VIL  
0
+0.8  
OVDD  
V
Output Logic High  
(3.3V PCI receivers)  
VOH  
VOH  
VOL  
VOL  
IIL1  
0.9OVDD  
V
Output Logic High  
(3.3V LVTTL, 5V tolerant receivers)  
OVDD  
+2.4  
-0.5  
0
V
Output Logic Low  
(3.3V PCI receivers)  
0.35OVDD  
V
Output Logic Low  
(3.3V LVTTL, 5V tolerant receivers)  
+0.4  
0
V
Input Leakage Current  
(no pull-up or pull-down)  
0
μA  
Input Leakage Current  
(with internal pull-down)  
IIL2  
IIL4  
0
200  
-325  
μA  
μA  
V
5V Tolerant I/O Input Current  
±10  
2
Input Max Allowable Overshoot  
(1.8V CMOS receivers)  
VIMAO1.8  
VDD + 0.6  
Input Max Allowable Overshoot  
(3.3V LVTTL, 5V tolerant receivers)  
VIMAO  
VIMAU  
VOMAO  
VOMAU  
+5.5  
+5.5  
V
V
V
V
Input Max Allowable Undershoot  
(3.3V LVTTL, 5V tolerant receivers)  
-0.6  
-0.6  
Output Max Allowable Overshoot  
(3.3V LVTTL, 5V tolerant receivers)  
Output Max Allowable Undershoot  
(3.3V LVTTL, 5V tolerant receivers)  
AMCC  
37  
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