Revision 2.04 – September 7, 2007
405GPr – Power PC 405GPr Embedded Processor
Data Sheet
Signal Functional Description (Sheet 5 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
Description
I/O
Type
Notes
External Master Peripheral Interface
Peripheral clock to be used by an external master and by
synchronous peripheral slaves.
5V tolerant
PerClk
ExtReset
HoldReq
HoldAck
ExtReq
ExtAck
O
O
I
3.3V LVTTL
Peripheral reset to be used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
Hold Request, used by an external master to request ownership of
the peripheral bus.
5V tolerant
3.3V LVTTL
1, 5
6
Hold Acknowledge, used by the PPC405GPr to transfer ownership of
peripheral bus to an external master.
5V tolerant
3.3V LVTTL
O
I
ExtReq is used by an external master to indicate it is prepared to
transfer data.
5V tolerant
3.3V LVTTL
1
5V tolerant
3.3V LVTTL
ExtAck is used by the PPC405GPr to indicate a data transfer cycle.
O
I
6
Used by an external master to indicate the priority of a given external
master tenure.
5V tolerant
3.3V LVTTL
HoldPri
BusReq
PerErr
1
Used when the PPC405GPr needs to regain control of peripheral
interface from an external master.
5V tolerant
3.3V LVTTL
O
I
An input used to indicate to the PPC405GPr that an external slave
peripheral error occurred.
5V tolerant
3.3V LVTTL
1, 5
Internal Peripheral Interface
Serial Clock used to provide an alternate clock to the internally
generated serial clock. Used in cases where the allowable internally
generated baud rates are not satisfactory. This input can be
individually connected to either UART.
5V tolerant
3.3V LVTTL
UARTSerClk
I
1
5V tolerant
UART0_Rx
UART0_Tx
UART0 Serial Data In.
I
O
I
1
6
1
1
1
6
6
1
1
3.3V LVTTL
5V tolerant
3.3V LVTTL
UART0 Serial Data Out.
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
UART1 Serial Data In.
5V tolerant
3.3V LVTTL
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0_RI
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
O
O
I
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
UART1_Rx
I
34
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
