欢迎访问ic37.com |
会员登录 免费注册
发布采购

PPC405GP-3DE266CZ 参数 Datasheet PDF下载

PPC405GP-3DE266CZ图片预览
型号: PPC405GP-3DE266CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 405GP嵌入式处理器 [Power PC 405GP Embedded Processor]
分类和应用: PC
文件页数/大小: 59 页 / 1340 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号PPC405GP-3DE266CZ的Datasheet PDF文件第49页浏览型号PPC405GP-3DE266CZ的Datasheet PDF文件第50页浏览型号PPC405GP-3DE266CZ的Datasheet PDF文件第51页浏览型号PPC405GP-3DE266CZ的Datasheet PDF文件第52页浏览型号PPC405GP-3DE266CZ的Datasheet PDF文件第54页浏览型号PPC405GP-3DE266CZ的Datasheet PDF文件第55页浏览型号PPC405GP-3DE266CZ的Datasheet PDF文件第56页浏览型号PPC405GP-3DE266CZ的Datasheet PDF文件第57页  
Revision 2.03 – September 7, 2007  
405GP – Power PC 405GP Embedded Processor  
Data Sheet  
I/O Specifications—133 and 200MHz  
Notes:  
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the  
command is used by SDRAM.  
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.  
3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP  
IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,  
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.  
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.  
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.  
Input (ns)  
Output (ns)  
Output Current (mA)  
Signal  
Clock  
Notes  
Setup Time Hold Time  
Valid Delay  
(TOV max)  
Hold Time  
(TOH min)  
I/O H  
(minimum)  
I/O L  
(minimum)  
(TIS min)  
(TIH min)  
SDRAM Interface  
BA1:0  
na  
na  
na  
na  
na  
na  
2
na  
na  
na  
na  
na  
na  
1
7.5  
6.2  
7.5  
5.2  
6.1  
6.2  
6.2  
7.6  
6.3  
7.5  
7.5  
1
1
1
1
1
1
1
1
1
1
1
19  
19  
19  
40  
19  
19  
19  
19  
19  
19  
19  
12  
12  
12  
25  
12  
12  
12  
12  
12  
12  
12  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
1, 2  
2
BankSel3:0  
CAS  
1, 2  
2
ClkEn0:1  
DQM0:3  
2
DQMCB  
2
ECC0:7  
2
MemAddr12:0  
MemData0:31  
RAS  
na  
2
na  
1
1, 2  
2
na  
na  
na  
na  
1, 2  
1, 2  
WE  
External Slave Peripheral Interface  
DMAAck0:3  
DMAReq0:3  
EOT0:3/TC0:3  
PerAddr0:31  
PerBLast  
na  
5
na  
1
8
na  
8
0
na  
0
12  
na  
12  
19  
12  
8
na  
8
PerClk  
PerClk  
PerClk  
PerClk  
PerClk  
dc  
4
dc  
1
10  
8
0
12  
8
4
1
0
PerCS0  
na  
na  
8
0
12  
8
PerClk  
PerCS1:7[GPIO10:16]  
PerData0:31  
PerOE  
6
na  
4
1
na  
1
10  
8
0
0
19  
12  
19  
12  
na  
12  
12  
8
PerClk  
PerClk  
PerClk  
PerClk  
PerClk  
PerClk  
PerPar0:3  
10  
8
0
12  
8
PerR/W  
4
1
0
PerReady  
9
1
na  
8
na  
0
na  
8
PerWBE0:3  
3
1
External Master Peripheral Interface  
BusReq  
ExtAck  
ExtReq  
ExtReset  
HoldAck  
HoldPri  
HoldReq  
PerClk  
na  
na  
5
na  
na  
1
8
7
0
0
12  
12  
na  
19  
12  
na  
na  
19  
na  
8
PerClk  
PerClk  
PerClk  
PerClk  
PerClk  
PerClk  
PerClk  
PLB Clk  
PerClk  
8
na  
8
na  
0
na  
12  
8
na  
na  
4
na  
na  
1
8
0
na  
na  
0.9  
na  
na  
na  
0.7  
na  
na  
na  
12  
na  
5
1
na  
3
na  
1
4
PerErr  
AMCC  
53  
 复制成功!