Revision 2.03 – September 7, 2007
405GP – Power PC 405GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment—413-Ball Package (Part 1 of 3)
Ball
Signal Name
Ball
B17
B18
Signal Name
Ball
D10
D11
Signal Name
PerCS5[GPIO14]
OVDD
Ball
G13
G15
Signal Name
PCIINT[PerWE]
OVDD
A1
GND
PCIAD0
A2
PerAddr4
PCIAD3
VDD
VDD
A3
PerAddr11
B19
Reserved
D12
G16
PCIReq3
A4
A5
PerAddr15
PerAddr18
GND
B20
B21
B22
B23
C1
PCIReq2
PCIReq1
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
E1
G17
G20
G21
G22
G23
H1
DrvrInh2
PCISErr
PCIReq5
PCIAD16
PCIAD18
PerData16
PerData22
Reserved
PerData31
PerR/W
GND
PCIReq0[Gnt]
PCIC0[BE0]
PCIClk
A6
PCIAD11
A7
PerAddr21
DMAAck3
PerAddr25
PerAddr27
OVDD
PCIGnt2
A8
PerPar3
A9
C2
EOT0/TC0
PerAddr3
Reserved
PCIAD9
A10
A11
A12
A13
A14
A15
C3
H2
C4
PerAddr5
PCIAD12
PCIAD15
PCIPErr
H3
PerAddr28
VDD
C5
PerAddr8
H4
C6
DMAReq3
PerCS4[GPIO13]
PerAddr16
H7
PerAddr29
DMAAck2
C7
PCIGnt3
H8
PerErr
OVDD
C8
PerData24
H9
OVDD
A16
A17
A18
A19
DMAReq1
DMAAck0
GND
C9
PerAddr17
PerCS7[GPIO16]
PerAddr2
E2
E3
Reserved
PerPar2
PerWBE3
TestEn
H10
H11
H13
H14
C10
C11
C12
PerCS1[GPIO10]
PCIAD13
E4
OVDD
PCIAD4
PerAddr24
E20
OVDD
A20
A21
A22
A23
B1
GPIO1[TS1E]
GPIO3[TS1O]
PCIAD10
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
D1
DMAReq0
GND
E21
E22
E23
F1
PCIParity
PCIIRDY
PCIC2[BE2]
GND
H15
H16
H17
H20
H21
H22
H23
J1
SysClk
DrvrInh1
PCIAD5
GND
Reserved
PCIAD6
PCIDevSel
PCIFrame
PCIAD17
PCIGnt5
PerWBE2
F2
PerData23
PerData29
PerPar1
B2
PerWBE1
PCIAD7
F3
B3
PerAddr6
GPIO2[TS2E]
PCIAD8
F4
B4
PerAddr9
F20
F21
F22
F23
G1
PCIReq4
PCITRDY
EMCTxD0
GND
PerData13
PerData21
PerData25
PerData28
OVDD
B5
PerAddr14
PerCS6[GPIO15]
PerAddr19
PerAddr20
PHYTxClk
PCIC1[BE1]
PCIStop
J2
B6
J3
B7
J4
B8
PerData27
PerData19
J7
OVDD
B9
DMAReq2
PerAddr22
PerAddr23
PerAddr26
PerAddr30
DMAAck1
D2
D3
D4
D5
D6
D7
PerData30
PerBLast
G2
G3
PerData20
PerData26
EOT1/TC1
PerAddr0
J8
B10
B11
B12
B13
B14
J9
PerClk
OVDD
PerWBE0
G4
J10
J11
J12
J13
PerCS3[GPIO12]
PerAddr7
G7
GND
PerAddr1
GND
G8
PerCS2[GPIO11]
OVDD
PerAddr10
G10
OVDD
B15
B16
J16
J17
J20
J21
J22
PCIAD1
PCIAD2
OVDD
D8
D9
PerAddr12
PerAddr13
VDD
G11
G12
N22
N23
P1
PerCS0
PerAddr31
PCIAD24
GND
J14
J15
T1
SysReset
BusReq
L20
L21
L22
L23
M1
OVDD
AVDD
T2
PerData3
EMCMDClk
EMCTxEn
EMCTxD2
PCIAD19
OVDD
PerData10
PerData5
HoldPri
T3
MemData31
MemData27
GPIO9[TrcClk]
P2
T4
PerData11
P3
T7
AMCC
27