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PPC405EXR-NSD533T 参数 Datasheet PDF下载

PPC405EXR-NSD533T图片预览
型号: PPC405EXR-NSD533T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA388, 27 X 27 MM, ROHS COMPLIANT, PLASTIC, MS-034C, EBGA-388]
分类和应用: 时钟外围集成电路
文件页数/大小: 76 页 / 1242 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.23 - January 28, 2009  
PPC405EX – PowerPC 405EX Embedded Processor  
Data Sheet  
Table 6. Signal Functional Description (Sheet 5 of 7)  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.  
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
Signal Name  
NAND Flash Interface  
NFALE  
Description  
I/O  
Type  
Notes  
Address latch enable.  
Chip select 0.  
O
O
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
NFCE0  
NFCE1:3  
Chip selects 1:3.  
Command latch enable.  
Data Bus  
O
1
NFCLE  
O
NFData00:15  
I/O  
Read/Busy. If low, indicates that Read/Erase command is in process.  
If high, indicates that the command is complete.  
NFRdyBusy  
I
3.3V LVTTL  
NFRE  
NFWE  
Read enable.  
Write enable.  
O
O
3.3V LVTTL  
3.3V LVTTL  
DDR1/2 SDRAM Interface  
2.5V (1.8V)  
SSTL2 Dr/Rcv  
MemData00:31  
MemAddr00:14  
RAS  
Memory data.  
I/O  
O
2.5V (1.8V)  
SSTL2 Dr/Rcv  
Memory address.  
2.5V (1.8V)  
SSTL2 Dr/Rcv  
Row address strobe.  
O
2.5V (1.8V)  
SSTL2 Dr/Rcv  
CAS  
Column address strobe.  
Clock enable.  
O
2.5V (1.8V)  
SSTL2 Dr/Rcv  
MemClkEn  
O
MemClkOut0  
MemClkOut0  
2.5V (1.8V)  
SSTL2 Dr/Rcv  
Differential DDR SDRAM clock output.  
O
Feedback driver. Connect directly to MemFBR with the minimum  
trace length.  
2.5V (1.8V)  
SSTL2 Dr/Rcv  
MemFBD  
MemFBR  
MemODT0:1  
DM0:4  
O
2.5V (1.8V)  
SSTL2 Dr/Rcv  
Feedback receiver. Connect externally to MemFBD.  
On-die termination.  
I
2.5V (1.8V)  
SSTL2 Dr/Rcv  
O
Write data byte lane mask. DM4 is the byte lane mask for the ECC  
byte lane.  
2.5V (1.8V)  
SSTL2 Dr/Rcv  
O
2.5V (1.8V)  
SSTL2 Dr/Rcv  
DQS0:4  
BA0:2  
Byte lane strobe. DQS4 is the strobe for the ECC lane.  
Bank address for up to eight banks.  
Bank select for up to two SDRAM memory banks.  
ECC check bit byte.  
I/O  
O
2.5V (1.8V)  
SSTL2 Dr/Rcv  
2.5V (1.8V)  
SSTL2 Dr/Rcv  
BankSel0:1  
ECC0:7  
WE  
O
2.5V (1.8V)  
SSTL2 Dr/Rcv  
I/O  
O
2.5V (1.8V)  
SSTL2 Dr/Rcv  
Write enable.  
AMCC Proprietary  
43  
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