Revision 1.23 - January 28, 2009
PPC405EX – PowerPC 405EX Embedded Processor
PCI Express (PCI-E) I/O Specifications
Data Sheet
The following tables provide the required I/O timing information regarding the use of the PCI Express interface on
this chip.
Table 28. PCI-E Receiver I/O Specifications
Parameter
Minimum
Maximum
Units
ps
Notes
Unit Interval (UI)
399.88
175
0.4
-
400.12
Differential Rx peak-peak voltage
Receiver eye time opening
1200
-
mV
UI
Maximum time delta between median and deviation from median
Rx differential return loss
0.3
-
UI
10
dB
dB
Ω
Common mode Rx return loss
6
-
Receiver DC common mode impedance
DC differential impedance
40
60
120
150
-
80
Ω
Rx AC common mode voltage
-
mV
kΩ
ns
DC Input CM input impedance during reset or power down
Electrical idle detect threshold
200
65
125
Table 29. PCI-E Reference Clock I/O Specifications
Parameter
Minimum
100
Maximum
100
Units
MHz
ppm
%
Notes
PCI_E reference clock frequency (PCIEnClkC and PCIEnClkT )
1
Accuracy
-300
+300
55
Duty cycle
45
-6
-
86
ps
3
2
Peak-to-peak jitter for 1E-6 BER (1 x 10 bit error rate)
Spread Spectrum Clock (SSC) frequency
Common mode voltage
Differential signal amplitude
Notes:
30
0
33
kHz
mV
mV
1600
1600
200
1. The PCI-E reference clock frequency specification does not include +/- 300ppm accuracy specification.
2. The data rate can be modulated from +0.5% to −0.5% of the nominal data rate frequency, at a modulation rate in the range not
exceeding 30kHz–33kHz. The +/- 600ppm requirement remains which requires the two communicating ports to be modulated so that
they never exceed a total of 600ppm difference. For most implementations, this requires that both ports have the same bit rate clock
source when the data is modulated with an SSC.
3. 1E-6 is the probability that the jitter is greater than 86ps peak-to-peak.
AMCC Proprietary
69
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
