Revision 1.12 - Novenber 20, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
NAND Flash Interface
NFALE
Description
I/O
Type
Notes
Address latch enable.
Chip select 0.
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
NFCE0
NFCE1:3
Chip selects 1:3.
Command latch enable.
Data Bus
O
1
NFCLE
O
NFData00:15
I/O
Read/Busy. If low, indicates that Read/Erase command is in process.
If high, indicates that the command is complete.
NFRdyBusy
I
3.3V LVTTL
NFRE
NFWE
Read enable.
Write enable.
O
O
3.3V LVTTL
3.3V LVTTL
DDR1/2 SDRAM Interface
2.5V (1.8V)
MemData00:31
MemAddr00:14
RAS
Memory data.
I/O
O
SSTL2 Dr/Rcv
2.5V (1.8V)
Memory address.
SSTL2 Dr/Rcv
2.5V (1.8V)
Row address strobe.
O
SSTL2 Dr/Rcv
2.5V (1.8V)
CAS
Column address strobe.
Clock enable.
O
SSTL2 Dr/Rcv
2.5V (1.8V)
MemClkEn
O
SSTL2 Dr/Rcv
MemClkOut0
MemClkOut0
2.5V (1.8V)
Differential DDR SDRAM clock output.
Feedback driver.
O
SSTL2 Dr/Rcv
2.5V (1.8V)
MemFBD
MemFBR
MemODT0:1
DM0:4
O
SSTL2 Dr/Rcv
2.5V (1.8V)
Feedback receiver. Connect externally to MemFBD.
On-die termination.
I
SSTL2 Dr/Rcv
2.5V (1.8V)
O
SSTL2 Dr/Rcv
Write data byte lane mask. DM4 is the byte lane mask for the ECC
byte lane.
2.5V (1.8V)
O
SSTL2 Dr/Rcv
2.5V (1.8V)
DQS0:4
BA0:2
Byte lane strobe. DQS4 is the strobe for the ECC lane.
Bank address for up to eight banks.
Bank select for up to two SDRAM memory banks.
ECC check bit byte.
I/O
O
SSTL2 Dr/Rcv
2.5V (1.8V)
SSTL2 Dr/Rcv
2.5V (1.8V)
BankSel0:1
ECC0:7
WE
O
SSTL2 Dr/Rcv
2.5V (1.8V)
I/O
O
SSTL2 Dr/Rcv
2.5V (1.8V)
Write enable.
SSTL2 Dr/Rcv
AMCC Proprietary
43