Revision 1.12 - Novenber 20, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
PCI Express Interface (n = 0 and 1)
PCIEnATB
Analog Test Bus for manufacturing test.
O
I
CML
CML
PCIEnClkC
PCIEnClkT
Differential input for external reference clock.
5
External reference resistor. Attach a 1.37 kΩ, 1% resistor between
RExt and RExtG to provide the reference for both the bias currents
and the impedance calibration circuitry.
PCIEnRExt
I/O
CML
PCIEnRExtG
PCIEnRx
PCIEnRx
Differential receiver for received serial data.
Differential driver for transmitted serial data.
I
LVDS receiver
LVDS driver
PCIEnTx
PCIEnTx
O
Interrupts Interface
IRQ0:2
External interrupt requests.
External interrupt requests.
External interrupt requests.
External interrupt requests.
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
IRQ3:5
1
1
IRQ6
IRQ7:9
JTAG Interface
TCK
Test clock.
I
I
3.3V LVTTL
1
3.3V LVTTL
w/pull-up
TDI
Test data in.
1, 4
TDO
TMS
Test data out.
Test mode select.
O
I
3.3V LVTTL
3.3V LVTTL
w/pull-up
1
Test reset. Must be low at power-on to initialize the JTAG controller
and for normal operation of the PPC405EX.
3.3V LVTTL
w/pull-up
TRST
I
1, 5
40
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
