Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
ADDRESS MAP SUPPORT
Data Sheet
The NPe405H incorporates two separate address maps. The first is a fixed processor address map that serves the
PowerPC family of processors. This address map defines the possible contents of various address regions which
the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are
accessed by software running on the NPe405H processor through the use of mtdcr and mfdcr commands.
SYSTEM ADDRESS MAP
Table 1. System Address Map 4GB Total System Memory
Function
Subfunction
Start Address
0x00000000
0xE8010000
0xEC000000
0xEEE00000
0xEF500000
0xEF900000
End Address
0xE7FFFFFF
0xE87FFFFF
0xEEBFFFFF
0xEF3FFFFF
0xEF5FFFFF
0xFFFFFFFF
Size
3712MB
8MB
SDRAM, External peripherals, and PCI
memory
44MB
6MB
General use
Note: Any of the address ranges listed at
right may be use for any of the above
functions.
1MB
263MB
1
0xFFE00000
0xFFFE0000
0xFFFFFFFF
0xFFFFFFFF
2MB
External peripheral bus boot
Boot-up
PCI
2
128KB
PCI boot
PCI I/O
0xE8000000
0xE8800000
0xEEC00000
0xEED00000
0xEF400000
0xEF600300
0xEF600400
0xEF600500
0xEF600600
0xEF600700
0xEF600780
0xEF600800
0xEF600900
0xEF600A00
0xEF600B00
0xEF600C10
0xEF610000
0xEF620000
0xE800FFFF
0xEBFFFFFF
0xEEC00007
0xEED00003
0xEF40003F
0xEF600307
0xEF600407
0xEF60051F
0xEF60063F
0xEF60077F
0xEF6007FF
0xEF6008FF
0xEF6009FF
0xEF600AFF
0xEF600BFF
0xEF600C1F
0xEF61FFFF
0xEF62FFFF
64KB
56MB
8B
PCI I/O
Configuration registers
Interrupt Acknowledge and special cycle
Local configuration registers
UART0
4B
64B
8B
UART1
8B
IIC0
32B
OPB arbiter
64B
GPIO0 controller registers
GPIO1 controller registers
Ethernet MAC 0 registers
Ethernet MAC 1 registers
Ethernet MAC 2 registers
Ethernet MAC 3 registers
ZMII control registers
HDLCEX
128B
128B
256B
256B
256B
256B
16B
Internal peripherals
64KB
64KB
HDLCMP
Notes:
1. When external peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.
2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above.
3. After the boot process, software may reassign the boot memory regions for other uses.
4. All address ranges not listed above are reserved.
AMCC Proprietary
DS2011
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
