Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM
Figure 1. NPe405H Embedded Controller Functional Block Diagram
Clock
Control
Reset
See Peripheral Interface
Power
Mgmt
Universal
Interrupt
Controller
x2
DCRs
Timers
MMU
GPIO
x2
UART
x2
PPC405
Processor Core
IEC
IIC
DCR Bus
Trace
ICU
JTAG
DCU
16KB
I-Cache
8KB
D-Cache
On-chip Peripheral Bus (OPB)
Arb
DMA
OPB
Bridge
Controller
(4-Channel)
Processor Local Bus (PLB)
Ethernet
x4
MAL0
MAL1
HDLCEX
External
Bus
Controller
External
SDRAM
Controller
Bus Master
PCI Bridge
MAL2
Controller
ZMII
HDLCMP
13-bit addr
32-bit data
32-bit addr
32-bit data
66 MHz max (async)
Two
32-channel
ports
8
MII, RMII,
SMII
single-channel
ports
The NPe405H is designed using the IBM Microelectronics Blue Logic™ methodology in which major functional
blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way to
generate complex ASICs using IBM CoreConnect™ Bus Architecture.
6
DS2011
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
