Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
I/O SPECIFICATIONS(A)—133 AND 200 MHZ
Table 15. I/O Specifications—133 and 200MHz (Sheet 1 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM. Output times in table are in cycle 1.
3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(maximum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay Hold Time
(TIS min)
(TIH min)
(TOV max)
(TOH min)
Ethernet Interface
EMC0MDClk
n/a
n/a
0.0
n/a
n/a
12
12
8
8
1, async
1
1 OPB clock 1 OPB Clock
period + 10ns
EMC0MDIO
100
EMC0MDClk
PHYTX
period
EMC0TxD0:3
[EMC0Tx0:1D0:1]
[EMC0Tx0:3D]
12.4
7.0
5.0
4.1
2.3
1.5
n/a
n/a
n/a
n/a
12
12
8
8
1
EMC0TxEn
[EMC0Tx0En]
[EMC0Sync]
14.4
7.0
5.0
4.3
2.3
1.5
PHYTX
PHYTX
1
1
EMC0TxErr[EMC0Tx1En]
[EMC1TxD0][EMC1Tx2D0]
[EMC1TxD1][EMC1Tx2D1]
[EMC1TxD2][EMC1Tx3D0]
[EMC1TxD3][EMC1Tx3D1]
[EMC1TxEn][EMC1Tx2En]
[EMC1TxErr][EMC1Tx3En]
PHY0Col[PHY0Rx1Er]
PHY0CrS[PHY0CrS0DV]
PHY0RxClk
n/a
n/a
n/a
n/a
13.6[7.1]
[15.0][8.2]
[15.0][8.3]
[15.1][8.2]
[15.0][8.2]
[16.4][8.2]
[16.5][8.3]
n/a
4.0[2.4]
[4.8][2.5]
[4.8][2.5]
[4.8][2.5]
[4.8][2.5]
[4.8][2.5]
[4.8][2.5]
n/a
12
12
12
12
12
12
12
n/a
n/a
n/a
8
8
n/a
n/a
8
n/a
n/a
8
n/a
n/a
8
n/a
n/a
8
n/a
n/a
8
async[1.1]
async[1.0]
n/a
async[0.9]
async[1.3]
n/a
n/a
n/a
n/a
1
1
n/a
n/a
n/a
n/a
1, async
PHY0RxD0:3
[PHY0Rx0:1D0:1]
[PHY0Rx0:3D]
1.7
1.1
1.1
1.6
0.9
0.2
n/a
n/a
n/a
n/a
PHYRX
1
PHY0RxDV[PHY0CRS1DV]
PHY0RxErr[PHY0Rx0Er]
PHY0TxClk[PHY0RefClk]
[PHY1RxD0][PHY1Rx2D0]
[PHY1RxD1][PHY1Rx2D1]
[PHY1RxD2][PHY1Rx3D0]
[PHY1RxD3][PHY1Rx3D1]
[PHY1Col][PHY1Rx3Er]
[PHY1CrS][PHY1CrS2DV]
[PHY1RxClk]
1.5[1.0]
1.5[1.1]
n/a
1.7[1.1]
1.6[1.0]
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
PHYRX
PHYRX
1
1
1, async
[1.0][1.8]
[1.3][2.2]
[1.1][2.2]
[1.0][1.9]
[1.4][2.2]
[1.3][2.1]
n/a
[3.5][0.7]
[3.0][0.3]
[3.0][0.3]
[3.3][0.7]
[2.2][0.3]
[2.6][0.8]
n/a
[PHY1RxDV]
[PHY1CrS3DV]
[1.0]
[2.1]
[2.6]
[0.0]
n/a
n/a
n/a
n/a
[PHY1RxErr][PHY1Rx2Er]
[PHY1TxClk]
[1.0][1.9]
n/a
[3.2][0.6]
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
HDLCEX Interface
HDLCEXRxClk
n/a
n/a
1.4
0.6
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
HDLCEXRxDataA:B
HDLCEXRxFS
27.7
24.2
62
DS2011
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
