Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
I/O SPECIFICATIONS—ALL
Data Sheet
Table 14. I/O Specifications—All (Sheet 1 of 2)
Notes:
1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for
33MHz.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(maximum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay Hold Time
(T min)
(T min)
(T
OV
max)
(T min)
OH
IS
IH
PCI Interface
PCIAD00:31
PCIC0:3[BE3:0]
PCIClk
3.0
3.0
n/a
3.0
3.0
0.0
0.0
n/a
0.0
0.0
6.0
2.0
0.5
0.5
n/a
0.5
0.5
1.5
1.5
n/a
1.5
1.5
PCIClk
PCIClk
6
6.0
n/a
6.0
6.0
2.0
n/a
2.0
2.0
6
async
6
PCIDevSel
PCIFrame
PCIClk
PCIClk
6
PCIGnt0[Req]
PCIGnt1:5
n/a
n/a
6.0
2.0
0.5
1.5
PCIClk
6
PCIIDSel
3.0
n/a
3.0
3.0
3.0
0.0
n/a
0.0
0.0
0.0
n/a
6.0
6.0
6.0
6.0
n/a
2.0
2.0
2.0
2.0
n/a
0.5
0.5
0.5
0.5
n/a
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
6
PCIINT[PerWE]
PCIIRDY
async
6
6
6
PCIParity
PCIPErr
PCIReq0[Gnt]
PCIReq1:5
5.0
0.0
n/a
n/a
n/a
n/a
PCIClk
6
PCIReset
PCISErr
PCIStop
PCITRDY
n/a
3.0
3.0
3.0
n/a
0.0
0.0
0.0
6.0
6.0
6.0
6.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
6
6
Internal Peripheral Interface
IICSCL
async
async
async
async
async
n/a
async
async
async
async
async
n/a
async
async
n/a
async
async
n/a
17
17
11
11
n/a
n/a
n/a
8
IICSDA
[UART0_CTS]
[UART0_DCD]
[UART0_DSR]
[UART0_DTR]
[UART0_RI]
n/a
n/a
n/a
12
n/a
n/a
n/a
n/a
async
n/a
async
n/a
async
n/a
async
n/a
n/a
12
n/a
8
[UART0_RTS]
UART0_Rx
async
n/a
async
n/a
async
n/a
async
n/a
n/a
12
n/a
8
UART0_Tx
async
n/a
async
n/a
[UART1_CTS]
[UART1_DCD]
[UART1_DSR]
[UART1_DTR]
[UART1_RI]
async
async
async
n/a
async
async
async
n/a
n/a
n/a
n/a
12
n/a
n/a
n/a
8
n/a
n/a
n/a
n/a
async
n/a
async
n/a
async
n/a
async
n/a
n/a
12
n/a
8
[UART1_RTS]
UART1_Rx
async
n/a
async
n/a
async
n/a
async
n/a
n/a
12
n/a
8
UART1_Tx
async
n/a
async
n/a
UARTSerClk
Interrupts Interface
[IRQ0:6]
async
async
n/a
n/a
async
async
n/a
n/a
n/a
n/a
60
DS2011
AMCC Proprietary