nP3740
nPcore Architecture
AMCC's software programmable nPcores
are built from the ground up for both
packet- and cell-based networking data
plane operations. The nP3740 supports
5-Gbps full-duplex operation utilizing a
cluster of three nPcores. Each nPcore has 24
separate tasks, yielding a total of 72, which
are all available for either ingress or egress
processing. The nPcores implement
zero-cycle task switching and zero-cycle
branching for enhanced performance.
The nPcores are surrounded by on-chip
coprocessing engines to accelerate
sophisticated network processing
functions, such as packet classification,
route and context searching, statistics
gathering, metering, policing, and packet
transformations. The nPcores, in
combination with these on-chip
coprocessing engines, implement Network
Instruction Set Computing (NISC)
Architecture. This NISC architecture
dramatically reduces the number of lines of
code required to implement many
advanced networking tasks.
A key addition to the nP37xx architecture is
the exception channel processing that
provides flexibility in handling packets that
require increased processing time. This
exception channel handles special packets
through a secondary path, without
affecting the deterministic line-rate
performance of the regular packets in the
primary path. The addition of a special
preprocessor, the Channel Service Module
(CSM), offers a store-and-forward capability
to nP37xx architecture. The CSM is able to
buffer incoming traffic according to the
level of channelization of the line interfaces.
A sizable CSM buffer absorbs very large
bursts in the incoming traffic without data
losses.
Single-Stage, Single-Image
Programming
AMCC's nPcore architecture implements a
simple single-stage programming model.
In this model each cell or packet is
processed in its entirety, from start to finish,
by a single task in a single nPcore. With this
single-stage model, the entire data flow
algorithm can be created as a single
complete software program, just as it
would be on a non-multiprocessor system,
allowing the same program image to be
executed identically by each task on each
nPcore. This approach greatly simplifies
programming while optimizing
performance.
Traffic Management
The traffic management block in the
nP3740 leverages AMCC’s expertise and
technology from the nPX5700 family of
traffic managers.
The nP3740 implements a hierarchical
scheduling architecture to provide multiple
levels of bandwidth provisioning and
per-subscriber guarantees. This hierarchy
consists of four logical levels: flow, pipe,
subport and port. Minimum and maximum
bandwidth control can be configured on
multiple levels. WFQ and Strict Priority
scheduling algorithms are also
implemented by the traffic management
block. For ATM applications, non-real-time
and real-time CBR and VBR connections can
be configured for a desired subset of flows.
Input Admission Control
Sophisticated cell and packet admission
controls are configurable in the nP3740.
This includes execution of standard discard
mechanisms such as WRED, EPD, and TPD
in hardware or the option to perform
variations in software.
QDR SRAM QDR SRAM
QDR SRAM QDR SRAM
RLDRAM II
RLDRAM II
RLDRAM II
RLDRAM II
Fiber Optic
Transceiver
SONET
CDR
Ohio
S4806
OC-12/48
ATM/POS
Framer
RLDRAM II
RLDRAM II
UT3
nP3740
Network
Processor
SPI-4
PRS
Fabric
Interface
nP3740 OC-48 ATM/POS Line Card
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
