nP3740
nP3740 Highlights
Interfaces
• Line Interfaces – cell and packet
SPI-3/UT-3
nP3740
2
GE
1
SPI-4.2
1
– Context Memory:
Two banks of 36-bit RLDRAM II
operating at up to 250 MHz (32 Gbps
with ECC)
– Channel Service Memory:
One bank of 36-bit QDR-II SRAM
operating at up to 250 MHz
– Flow Database Memory:
Two banks of 18-bit QDR-II SRAM
operating at up to 250 MHz
CPU Interfaces: PowerPC and Gigabit
Ethernet
External Search Interface
– Compliant with NPF
– Backward compatibility mode with
existing TCAMs
Debug port
JTAG port
High Performance nPcore
• Three nPcores at up to 700 MHz
Integrated Coprocessors
• Policy Engine for efficient packet
classification
• Special Purpose Unit (SPU) for per-flow
policing
• Hashing Unit
• On-Chip Debugger (OCD)
Integrated Traffic Manager
• Hierarchical Traffic Manager with
fine-grained flow-based traffic
management
• Leverages field-proven nPX5710 and
nPX5720 technology
• Fabric Interface: OIF SPI-4 Phase 2
– 800 MHz
• External Memory Interfaces:
RLDRAM II memory controllers
– Payload Memory:
Two banks of 36-bit RLDRAM II
operating at up to 250 MHz (32 Gbps
with ECC)
•
•
•
•
18
36
36
QDR
SPU
36
36
36
36
RLDRAM
DRAM
Scratch
Pad
NPF(QDR)
SPI3/UT3
Policy
Engine
DRAM/SRAM
RLDRAM
XM I
XSC
Cache
Hash
Engine
Line Interfaces
SPI3/UT3
3 nPcores
@ 700 MHz
nPcore
@ 700 MHz
24 Tasks
72 Tasks
FE/GE
M ACs
Soft TM
Statistics
Engine
Traffic
Manager
Queuing
Scheduling
FABRIC INTERFACE
M em ory Access Unit
SPI4.2
GE
(Line/CPU)
Line
Interfaces
(CSM)
HOST CPU
HOST CPU
Packet Transform
Packet Transform
Engine
Engine
(PTE)
(PTE)
DEBUG
DEBUG
FCN
JTAG
16-bit
nP3740 Block Diagram
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
