IBM PowerPC 403GCX
Table 4. 403GCX Signal Descriptions
Signal
I/O
Type
Pin Ball
Name
Function
CS2
CS3
153 D5
152 B5
O
SRAM Chip Select 2. See description of CS0 but controls bank 2.
SRAM Chip Select 3. See description of CS0 but controls bank 3.
O
O
CS4/RAS3 151 C5
Chip Select 4/ DRAM Row Address Select 3. When bank register 4
is configured to control an SRAM bank, CS4/RAS3 functions as a
chip select. When bank register 4 is configured to control a DRAM
bank, CS4/RAS3 is the row address select for that bank.
CS5/RAS2 148 B6
CS6/RAS1 147 C6
CS7/RAS0 146 A6
O
O
O
Chip Select 5/ DRAM Row Address Select 2. See description of
CS4/RAS3 but controls bank 5.
Chip Select 6/ DRAM Row Address Select 1. See description of
CS4/RAS3 but controls bank 6.
Chip Select 7/ DRAM Row Address Select 0. See description of
CS4/RAS3 but controls bank 7.
D0
42
43
44
45
46
47
48
51
52
53
54
55
56
57
58
62
63
64
65
66
67
68
N2
P2
N3
P3
N4
M4
P4
P5
M5
L5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data bus bit 0 (most significant bit).
Data bus bit 1.
D1
D2
Data bus bit 2.
D3
Data bus bit 3.
D4
Data bus bit 4.
D5
Data bus bit 5.
D6
Data bus bit 6.
D7
Data bus bit 7.
D8
Data bus bit 8.
D9
Data bus bit 9.
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
N6
P6
M6
L6
Data bus bit 10.
Data bus bit 11.
Data bus bit 12.
Data bus bit 13.
Data bus bit 14.
Data bus bit 15.
Data bus bit 16.
Data bus bit 17.
Data bus bit 18.
Data bus bit 19.
Data bus bit 20.
Data bus bit 21.
N7
M7
P8
N8
L8
P9
M9
N9
10
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
