Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Mailbox Overview
Data Sheet
Add-On incoming and outgoing mailbox interrupts are
enabled/disabled in the Add-On Interrupt Control/Sta-
tus Register (AINT). The mailboxes can generate the
Add-On IRQ# interrupt under two conditions (individu-
ally enabled). For an incoming mailbox full interrupt,
IRQ# is asserted on the rising edge of the Add-On
clock after the PCI mailbox write completes. For an
outgoing mailbox empty interrupt, IRQ# is asserted on
the rising edge of the Add-On clock after the PCI mail-
box read completes. IRQ# is deasserted one Add-On
clock cycle after the mailbox interrupt is serviced (by
writing a 1 to the proper interrupt source bit).
CONFIGURATION
The PCI interface and the Add-On interface each have
one incoming mailbox (IMB or AIMB) and one outgo-
ing mailbox (OMB or AOMB) along with a single
mailbox status register (MBEF or AMBEF). The outgo-
ing mailbox is read/write, the incoming mailbox and
the mailbox status registers are read-only.
The following sections discuss the registers associ-
ated with the mailboxes and accesses required for
different modes of mailbox operation.
Mailbox Status
8-Bit and 16-Bit Add-On Interfaces
Every byte in each mailbox has a status bit in the Mail-
box Empty/Full Status Registers (MBEF and AMBEF).
Writing a particular byte into the outgoing mailbox sets
the corresponding status bit in both the MBEF and
AMBEF registers. A read of a ‘full’ byte in a mailbox
clears the status bit. The MBEF and AMBEF are read-
only. Status bits cannot be cleared by writes to the sta-
tus registers.
Some Add-On designs may implement an 8-bit or 16-
bit bus interface. The mailboxes do not require a 32-bit
Add-On interface for all the bytes to be read/written.
For 8-bit interfaces, the 8-bit data bus may be exter-
nally connected to all 4 bytes of the 32-bit Add-On
interface (DQ 31:24, 23:16, 15:8, 7:0 are all con-
nected). The Add-On device reading or writing the
mailbox registers may access all mailbox bytes by
cycling through the Add-On byte enable inputs (only
one byte enable may be active at a time). A similar
solution applies to 16-bit Add-On buses. This solution
works for Add-On designs which always use just one
bus width (8-bit or 16-bit).
The S5320 allows the mailbox status bits to be reset
through software. The PCI Bus Reset Control PCI
Operation Register (RCR) and the Add-On Reset Con-
trol Add-On Operation Register (ARCR) each have a
bit to reset mailbox status. Writing a 1 to Mailbox Flag
Reset bit in the RCR or the ARCR register immedi-
ately clears all bits in the both the MBEF and AMBEF
registers. Writing a 0 has no effect. The Mailbox Flag
Reset bit is write-only.
If the DQMODE pin is high, indicating a 16-bit Add-On
interface, the previous solution may be used to imple-
ment an 8-bit interface. The only modification needed
is that BE3(= ADR1) must be toggled after the first two
accesses to steer the S5320 internal data bus to
access the upper 16 bits of the mailboxes.
The flag bits should be monitored when transferring
data through the mailboxes. Checking the mailbox sta-
tus before performing an operation prevents data from
being lost or corrupted. The following sequences are
suggested for PCI mailbox operations using status
polling (interrupts disabled).
Figure 56. Input/Output Mode (MDMODE=0)
ADCLK
LOAD#
S5320
Driving
Turn
Around
WRITE
DATA
Turn
Around
S5320
Driving
MD[0:7]
Figure 57. Input Mode (MDMODE=1)
ADCLK
LOAD#
MD[0:7]
WRITE
DATA
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