Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Mailbox Overview
MAILBOX OVERVIEW
Data Sheet
FUNCTIONAL DESCRIPTION
The S5320 has two 32-bit mailbox registers. These
mailboxes are useful for passing command and status
information between the Add-On and the PCI bus. The
PCI interface has one incoming mailbox (Add-On to
PCI) and one outgoing mailbox (PCI to Add-On). The
Add-On interface has one incoming mailbox (PCI to
Add-On) and one outgoing mailbox (Add-On to PCI).
The PCI incoming and Add-On outgoing mailboxes
are the same, internally. The Add-On incoming and
PCI outgoing mailboxes are also the same, internally.
Figure 54 shows a block diagram of the PCI to Add-On
mailbox registers. Add-On incoming mailbox read
accesses pass through an output interlock register.
This prevents a PCI bus write to a PCI outgoing mail-
box from corrupting data being read by the Add-On.
Figure 55 shows a block diagram of the Add-On to PCI
mailbox registers. PCI incoming mailbox reads also
pass through an interlocking mechanism. This pre-
vents an Add-On write to an outgoing mailbox from
corrupting data being read by the PCI bus. The follow-
ing sections describe the mailbox flag functionality and
the mailbox interrupt capabilities.
The mailbox status may be monitored in two ways.
The PCI and Add-On interfaces each have a mailbox
status register to indicate the empty/full status of data
bytes within the mailboxes. The mailboxes may also
be configured to generate interrupts to the PCI and/or
Add-On interface. The outgoing and the incoming
mailbox on each interface can be configured to gener-
ate interrupts.
Figure 54. PCI to Add-On Mailbox Register
OUTPUT
INTERLOCK
REGISTER
MAILBOX
REGISTER
PCI BUS
DQ
EN
DQ
EN
ADD-ON BUS
LOAD ENABLE
ADCLK
PCI CLK
RD#
SELECT#
ADR -MB
D
Q
VDD
ADCLK
R
S
DQ
PCI CLK
MAILBOX
FULL
100
DS1656
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