Revision 1.16 – July 19, 2006
440GR – PPC440GR Embedded Processor
I/O Specifications
Preliminary Data Sheet
Table 16. Peripheral Interface Clock Timings
Parameter
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
Min
–
Max
Units
MHz
ns
Notes
66.66
15
–
PCIClk input high time
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
EMCTxClk input frequency MII(RMII)
EMCTxClk period MII(RMII)
EMCTxClk input high time
EMCTxClk input low time
EMCRxClk input frequency MII(RMII)
EMCRxClk period MII(RMII)
EMCRxClk input high time
EMCRxClk input low time
160
160
–
ns
–
ns
2.5(5)
25(50)
MHz
ns
40(20)
400(200)
35% of nominal period
35% of nominal period
2.5(5)
–
ns
–
ns
25(50)
MHz
ns
40(20)
400(200)
35% of nominal period
35% of nominal period
–
–
ns
ns
PerClk (and OPB Clock) output frequency (for ext. master or
sync. slaves)
–
66.66
MHz
PerClk period
15
–
ns
ns
ns
PerClk output high time
PerClk output low time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
1000/(2TOPB1+2ns)
UARTSerClk input frequency
UARTSerClk period
–
MHz
ns
1
2TOPB+2
TOPB+1
–
–
1
1
1
2
UARTSerClk input high time
ns
T
OPB+1
UARTSerClk input low time
TmrClk1 input frequency
TmrClk1 period
–
ns
MHz
ns
–
100
10
–
TmrClk1 input high time
TmrClk1 input low time
Notes:
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
frequency is 66.66 MHz.
2. See Table 7 for information on the TmrClk2 signal.
AMCC Proprietary
65
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
