Revision 1.16 – July 19, 2006
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Address Maps
The PPC440GR incorporates two address maps. The first is a fixed processor System Memory Address Map. This
address map defines the possible contents of various address regions which the processor can access. The
second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC440GR processor through the use of mtdcr and mfdcr instructions.
Table 1. System Memory Address Map (Sheet 1 of 2)
Function
Local Memory1
EBC
Sub Function
Start Address
0 0000 0000
0 4000 0000
0 8000 0000
0 A000 0000
0 E000 0000
0 E800 0000
0 E801 0000
0 E880 0000
0 EC00 0000
0 EEC0 0000
0 EEC0 0008
0 EED0 0000
0 EED0 0004
0 EF40 0000
0 EF40 0040
End Address
0 3FFF FFFF
0 7FFF FFFF
0 9FFF FFFF
0 DFFF FFFF
0 E7FF FFFF
0 E800 FFFF
0 E87F FFFF
0 EBFF FFFF
0 EEBF FFFF
0 EEC0 0007
0 EECF FFFF
0 EED0 0003
0 EF3F FFFF
0 EF40 003F
0 EF4F FFFF
Size
DDR SDRAM
Reserved
EBC
1GB
512MB
1GB
PCI Memory
Reserved
PCI I/O
64KB
56MB
8B
Reserved
PCI I/O
Reserved
PCI
Configuration Registers
Reserved
PCI Interrupt Ack / Special Cycle
Reserved
4B
Local Configuration Registers
Reserved
64B
6
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
