Revision 1.16 – July 19, 2006
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Block Diagram
Figure 2. PPC440GR Functional Block Diagram
10
External
Interrupts
Clock
Control
Reset
Power
Mgmt
Timers
MMU
DCRs
UIC
PPC440
UART
x4
IIC
x2
BSC
GPIO
SPI
DCR Bus
Processor Core
Trace
JTAG
On-chip Peripheral Bus (OPB)
32KB
I-Cache
32KB
D-Cache
OPB
GPT
DMA
Performance
Monitor
Controller
Bridge
PLB3 (64 bits)
MAL
PLB
Bridge
PLB4 (128 bits)
Ethernet
10/100
x2
DMA
Controller
ZMII
External
NAND
Flash
PCI
Bridge
DDR SDRAM
Controller
Peripheral
Controller Controller
1 MII
or
66MHz max
- 32 bits
266MHz max
- 13-bit addr
- 32-bit data
66MHz max
- 30-bit addr
- 16-bit data
2 RMII
or
- 6 devices
2 SMII
™
The PPC440GR is a system on a chip (SOC) using IBM CoreConnect Bus Architecture.
AMCC Proprietary
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
