Revision 1.16 – July 19, 2006
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 8 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Trace Interface
Description
I/O
Type
Notes
3.3V tolerant
2.5V CMOS
TrcBS0:2
TrcClk
Trace branch execution status.
I/O
O
Trace data capture clock, runs at 1/4 the frequency of the
processor.
3.3V tolerant
2.5V CMOSL
Trace Execution Status is presented every fourth processor
clock cycle.
TrcES0:4
TrcTS0:6
I/O
I/O
3.3V LVTTL
3.3V tolerant
2.5V CMOS
Additional information on trace execution and branch status.
Power
VDD
1.5V supply—Logic voltage.
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
OVDD
SVDD
3.3V supply—I/O (except DDR SDRAM, Ethernet).
2.5V supply—SDRAM, Ethernet.
Ground.
GND
AVDD
1.5V—Filtered voltage for system PLLs (analog).
PLL (analog) voltage ground.
AGND
SAVDD
1.5V—Filtered voltage for memory PLL (analog).
PLL (analog) memory voltage ground.
SAGND
Other
To avoid noise pickup problems, most of these balls must be
connected in the board design as shown Table 6 on page 49.
Reserved
na
na
AMCC Proprietary
57
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
