Revision 1.16 – July 19, 2006
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 7 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
System Interface
Description
I/O
Type
Notes
SysClk
Main system clock input.
Clock
O
3.3V LVTTL
3.3V tolerant
2.5V CMOS
SysErr
Set to 1 when a machine check is generated.
Main system reset. External logic can drive this bidirectional
pin low (minimum of 16 cycles) to initiate a system reset. A
system reset can also be initiated by software. Implemented as
an open-drain output (two states; 0 or open circuit).
3.3V tolerant
2.5V CMOS
SysReset
I/O
1, 2
1, 4
Halt
Halt from external debugger.
I
I
3.3V LVTTL
3.3V tolerant
2.5V CMOS
TmrClk1
Processor timer external input clock.
This signal must be connected to a clock. It can be connected
to any available clocking signal in the frequency range of
32kHz to 100MHz including TmrClk1.
3.3V tolerant
2.5V CMOS
TmrClk2
I
General purpose I/O 0 through 63. To access these functions,
software must set DCR register bits.
GPIO00:63
I/O
Multiplex
TestEn
Test Enable.
I
I
I
I
I
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
3
RcvrInh
ModeCtrl
LeakTest
RefEn
Receiver Inhibit. Active only when TestEn is active.
Mode Control.
Leakage Test.
Reference Enable.
Driver Inhibit. Used for test purposes only. Tie up as specified
in Note 2 for normal operation.
3.3V tolerant
2.5V CMOS
DrvrInh1:2
PSROOut
I
2
Perf screen
ring osc
Module characterization and screening.
O
1, 3
56
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
