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EPM7256AEFC256-5 参数 Datasheet PDF下载

EPM7256AEFC256-5图片预览
型号: EPM7256AEFC256-5
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 5.5ns, 256-Cell, CMOS, PBGA256, FINE LINE, BGA-256]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 64 页 / 437 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000A Programmable Logic Device Data Sheet  
Figure 10 shows the typical output drive characteristics of MAX 7000A  
devices.  
Figure 10. Output Drive Characteristics of MAX 7000A Devices  
3.3 V  
2.5 V  
MAX 7000AE Devices  
MAX 7000AE Devices  
150  
150  
IOL  
IOL  
100  
50  
100  
50  
Typical IO  
Output  
Current (mA)  
Typical IO  
Output  
Current (mA)  
VCCINT = 3.3 V  
VCCIO = 3.3 V  
VCCINT = 3.3 V  
VCCIO = 2.5 V  
Temperature  
= 25 OC  
= 25 OC  
Temperature  
IOH  
IOH  
0
0
0
1
2
3
4
5
0
1
2
3
4
5
VO Output Voltage (V)  
VO Output Voltage (V)  
EPM7128A & EPM7256A Devices  
3.3 V  
2.5 V  
EPM7128A & EPM7256A Devices  
120  
120  
IOL  
IOL  
80  
40  
80  
40  
Typical IO  
Output  
Current (mA)  
Typical IO  
Output  
Current (mA)  
VCCINT = 3.3 V  
VCCIO = 3.3 V  
VCCINT = 3.3 V  
VCCIO = 2.5 V  
= 25OC  
= 25 OC  
Temperature  
Temperature  
IOH  
IOH  
0
0
0
1
2
3
4
5
1
2
3
4
5
VO Output Voltage (V)  
VO Output Voltage (V)  
MAX 7000A device timing can be analyzed with the Altera software, a  
variety of popular industry-standard EDA simulators and timing  
analyzers, or with the timing model shown in Figure 11. MAX 7000A  
devices have predictable internal delays that enable the designer to  
determine the worst-case timing of any design. The software provides  
timing simulation, point-to-point delay prediction, and detailed timing  
analysis for device-wide performance evaluation.  
Timing Model  
Altera Corporation  
31  
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