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EPM7256AEFC256-5 参数 Datasheet PDF下载

EPM7256AEFC256-5图片预览
型号: EPM7256AEFC256-5
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 5.5ns, 256-Cell, CMOS, PBGA256, FINE LINE, BGA-256]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 64 页 / 437 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000A Programmable Logic Device Data Sheet  
Figure 4. MAX 7000A Parallel Expanders  
Unused product terms in a macrocell can be allocated to a neighboring macrocell.  
From  
Previous  
Macrocell  
Preset  
Product-  
Term  
Select  
Matrix  
Macrocell  
Product-  
Term Logic  
Clock  
Clear  
Preset  
Product-  
Term  
Select  
Matrix  
Macrocell  
Product-  
Term Logic  
Clock  
Clear  
To Next  
Macrocell  
36 Signals 16 Shared  
from PIA Expanders  
Programmable Interconnect Array  
Logic is routed between LABs on the PIA. This global bus is a  
programmable path that connects any signal source to any destination on  
the device. All MAX 7000A dedicated inputs, I/O pins, and macrocell  
outputs feed the PIA, which makes the signals available throughout the  
entire device. Only the signals required by each LAB are actually routed  
from the PIA into the LAB. Figure 5 shows how the PIA signals are routed  
into the LAB. An EEPROM cell controls one input to a 2-input ANDgate,  
which selects a PIA signal to drive into the LAB.  
12  
Altera Corporation