MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture includes four dedicated inputs that can
be used as general-purpose inputs or as high-speed, global control
signals (clock, clear, and two output enable signals) for each
macrocell and I/ O pin. Figure 1 shows the architecture of EPM7032,
EPM7064, and EPM7096 devices.
Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram
INPUT/GLCK1
INPUT/GCLRn
INPUT/OE1
INPUT/OE2
LAB A
LAB B
8 to 16
8 to 16
36
36
Macrocells
1 to 16
Macrocells
17 to 32
I/O
Control
Block
I/O
Control
Block
8 to 16
I/O pins
8 to 16
I/O pins
16
16
8 to 16
8 to 16
LAB C
LAB D
PIA
8 to 16
8 to 16
36
36
Macrocells
33 to 48
Macrocells
49 to 64
I/O
Control
Block
I/O
Control
Block
8 to 16
I/O pins
8 to 16
I/O pins
16
16
8 to 16
8 to 16
Altera Corporation
7
ALTERA [ ALTERA CORPORATION ]
