MAX 7000 Programmable Logic Device Family Data Sheet
Table 20. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade -6 Speed Grade -7
Unit
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.4
0.4
0.8
3.5
0.8
2.0
2.0
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
(2)
FIN
Shared expander delay
Parallel expander delay
Logic array delay
SEXP
PEXP
LAD
LAC
IOE
OD1
Logic control array delay
Internal output enable delay
Output buffer and pad delay
(2)
C1 = 35 pF
2.0
2.5
7.0
Slow slew rate = off, V
= 5.0 V
CCIO
t
t
Output buffer and pad delay
Slow slew rate = off, V = 3.3 V
C1 = 35 pF (7)
C1 = 35 pF (2)
2.5
7.0
ns
ns
OD2
OD3
CCIO
Output buffer and pad delay
Slow slew rate = on,
V
= 5.0 V or 3.3 V
CCIO
t
t
t
Output buffer enable delay
Slow slew rate = off, V
C1 = 35 pF
4.0
4.5
9.0
4.0
4.5
9.0
ns
ns
ns
ZX1
ZX2
ZX3
= 5.0 V
= 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = off, V
C1 = 35 pF (7)
C1 = 35 pF (2)
CCIO
Output buffer enable delay
Slow slew rate = on
V
= 5.0 V or 3.3 V
CCIO
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output buffer disable delay
Register setup time
C1 = 5 pF
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XZ
3.0
1.5
2.5
0.5
3.0
2.0
3.0
0.5
SU
Register hold time
H
Register setup time of fast input
Register hold time of fast input
Register delay
(2)
(2)
FSU
FH
0.8
0.8
2.5
2.0
0.8
2.0
2.0
0.8
10.0
1.0
1.0
3.0
3.0
1.0
2.0
2.0
1.0
10.0
RD
Combinatorial delay
Array clock delay
COMB
IC
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
EN
GLOB
PRE
CLR
PIA
LPA
Low-power adder
(8)
32
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
