MAX 7000 Programmable Logic Device Family Data Sheet
Tables 19 through 26 show the MAX 7000 and MAX 7000E AC
operating conditions.
Table 19. MAX 7000 & MAX 7000E External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
-6 Speed Grade
-7 Speed Grade
Unit
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input to non-registered output
I/O input to non-registered output
Global clock setup time
C1 = 35 pF
C1 = 35 pF
6.0
6.0
7.5
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD1
PD2
SU
5.0
0.0
2.5
0.5
6.0
0.0
3.0
0.5
Global clock hold time
H
Global clock setup time of fast input (2)
FSU
FH
Global clock hold time of fast input
Global clock to output delay
Global clock high time
Global clock low time
(2)
C1 = 35 pF
4.0
6.5
4.5
7.5
CO1
CH
2.5
2.5
2.5
2.0
3.0
3.0
3.0
2.0
CL
Array clock setup time
Array clock hold time
ASU
AH
Array clock to output delay
Array clock high time
C1 = 35 pF
ACO1
ACH
ACL
CPPW
3.0
3.0
3.0
3.0
3.0
3.0
Array clock low time
Minimum pulse width for clear and
preset
(3)
t
t
f
Output data hold time after clock
Minimum global clock period
C1 = 35 pF (4)
1.0
1.0
ns
ns
ODH
CNT
CNT
6.6
6.6
8.0
8.0
Maximum internal global clock
frequency
(5)
151.5
125.0
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock
frequency
(5)
(6)
151.5
200
125.0
166.7
MHz
f
Maximum clock frequency
MHz
MAX
Altera Corporation
31
ALTERA [ ALTERA CORPORATION ]
