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EPM3064ATC44-7N 参数 Datasheet PDF下载

EPM3064ATC44-7N图片预览
型号: EPM3064ATC44-7N
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 7.5ns, 64-Cell, CMOS, PQFP44, TQFP-44]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 46 页 / 422 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 3000A Programmable Logic Device Family Data Sheet
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the
TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 3000A Device
The time required to program a single MAX 3000A device in-system can
be calculated from the following formula:
t
PROG
=
t
PPULSE
Cycle
PTCK
+ -------------------------------
-
f
TCK
where:
t
PROG
t
PPULSE
Cycle
PTCK
f
TCK
= Programming time
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
= Number of
TCK
cycles to program a device
=
TCK
frequency
The ISP times for a stand-alone verification of a single MAX 3000A device
can be calculated from the following formula:
t
VER
=
t
Cycle
VTCK
+ --------------------------------
VPULSE
f TCK
= Verify time
where:
t
VER
= Sum of the fixed times to verify the EEPROM cells
t
VPULSE
Cycle
VTCK
= Number of
TCK
cycles to verify a device
Altera Corporation
15