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EPM240T100C5N 参数 Datasheet PDF下载

EPM240T100C5N图片预览
型号: EPM240T100C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–24  
Chapter 5: DC and Switching Characteristics  
Referenced Documents  
Table 5–31. MAX II JTAG Timing Parameters (Part 2 of 2)  
Symbol  
Parameter  
Min  
Max  
25  
Unit  
ns  
tJSZX  
tJSXZ  
Update register high impedance to valid output  
Update register valid output to high impedance  
25  
ns  
Notes to Table 5–31:  
(1) Minimum clock period specified for 10 pF load on the TDOpin. Larger loads on TDOwill degrade the maximum TCK  
frequency.  
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V  
LVTTL/LVCMOS and 1.5-V LVCMOS, the tJPSU minimum is 6 ns and tJPCO, tJPZX, and tJPXZ are maximum values at 35 ns.  
Referenced Documents  
This chapter references the following documents:  
I/O Structure section in the MAX II Architecture chapter in the MAX II Device  
Handbook  
Hot Socketing and Power-On Reset in MAX II Devices chapter in the MAX II Device  
Handbook  
Operating Requirements for Altera Devices Data Sheet  
PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook  
Understanding and Evaluating Power in MAX II Devices chapter in the MAX II Device  
Handbook  
Understanding Timing in MAX II Devices chapter in the MAX II Device Handbook  
Using MAX II Devices in Multi-Voltage Systems chapter in the MAX II Device  
Handbook  
MAX II Device Handbook  
© Novermber 2008 Altera Corporation  
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