5–22
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Maximum Input and Output Clock Rates
Table 5–29 and Table 5–30 show the maximum input and output clock rates for
standard I/O pins in MAX II devices.
Table 5–29. MAX II Maximum Input Clock Rate for I/O
–3 Speed
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Standard
Grade
Unit
3.3-V LVTTL
Without Schmitt
Trigger
304
250
304
250
220
188
220
188
200
200
150
304
304
250
304
250
220
188
220
188
200
200
150
304
304
250
304
250
220
188
220
188
200
200
150
304
304
250
304
250
220
188
220
188
200
200
150
304
304
250
304
250
220
188
220
188
200
200
150
304
MHz
With Schmitt
Trigger
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
3.3-V LVCMOS
2.5-V LVTTL
Without Schmitt
Trigger
With Schmitt
Trigger
Without Schmitt
Trigger
With Schmitt
Trigger
2.5-V LVCMOS
Without Schmitt
Trigger
With Schmitt
Trigger
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V PCI
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
Table 5–30. MAX II Maximum Output Clock Rate for I/O
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
–7 Speed
Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V PCI
Grade
304
304
220
220
200
200
150
304
Grade
304
304
220
220
200
200
150
304
Unit
304
304
220
220
200
200
150
304
304
304
220
220
200
200
150
304
304
304
220
220
200
200
150
304
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MAX II Device Handbook
© Novermber 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
