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EPM240T100C5N 参数 Datasheet PDF下载

EPM240T100C5N图片预览
型号: EPM240T100C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–26
Chapter 2: MAX II Architecture
I/O Structure
shows how a column I/O block connects to the logic array.
Figure 2–21.
Column I/O Block Connection to the Interconnect
Column I/O
Block Contains
Up To 4 IOEs
data_in
[3..0]
4
4
Column I/O Block
data_out
[3..0]
4
I/O Block
Local Interconnect
OE
[3..0]
4
fast_out
[3..0]
Fast I/O
Interconnect LAB Column
Path Clock [3..0]
R4 Interconnects
LAB
LAB
LAB
LAB Local
Interconnect
C4 Interconnects
LAB Local
Interconnect
LAB Local
Interconnect
C4 Interconnects
Note to
(1) Each of the four IOEs in the column I/O block can have one
data_out
or
fast_out
output, one
OE
output, and one
data_in
input.
I/O Standards and Banks
MAX II device IOEs support the following I/O standards:
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI