9–16
Chapter 9: Using User Flash Memory in MAX II Devices
Software Support for UFM Block
Device Addressing
After the start condition, the master sends the address of the particular slave device it
is requesting. The four most significant bits (MSBs) of the 8-bit slave address are
usually fixed while the next three significant bits (A2, A1, A0) are device address bits
and define which device the master is accessing. The last bit of the slave address
specifies whether a read or write operation is to be performed. When this bit is set to
1, a read operation is selected. When this bit is set to 0, a write operation is selected.
The four MSBs of the slave address (A6, A5, A4, A3) are programmable and can be
defined on page 3 of the altufm MegaWizard Plug-In Manager. The default value for
these four MSBs is 1010. The next three significant bits are defined using the three A2,
A1, A0 input ports of the altufm_i2c megafunction. You can connect these ports to
input pins in the design file and connect them to switches on the board. The other
option is to connect them to VCC and GND primitives in the design file, which
conserves pins. Figure 9–14 shows the slave address bits.
Figure 9–14. Slave Address Bits
MSB
1
LSB
1- or 2-Kbit Memory Size
4-Kbit Memory Size (1)
8-Kbit Memory Size (2)
0
0
0
1
1
1
0
0
0
A
A
A
A
A
A R/W
0
2
2
2
1
1
MSB
1
LSB
a8 R/W
MSB
1
LSB
a9 a8 R/W
Notes to Figure 9–14:
(1) For the 4-Kbit memory size, the A0 location in the slave address becomes the MSB (a8) of the memory byte address.
(2) For the 8-Kbit memory size, the A0 location in the slave address becomes a8 of the memory byte address, while the
A1 location in the slave address becomes the MSB (a9) of the memory byte address.
After the master sends a start condition and the slave address byte, the altufm_i2c
logic monitors the bus and responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The altufm_i2c megafunction then
performs a read or write operation to/from the UFM, depending on the state of the
bit.
Byte Write Operation
The master initiates a transfer by generating a start condition, then sending the correct
slave address (with the R/W bit set to 0) to the slave. If the slave address matches, the
altufm_i2c slave acknowledges on the ninth clock pulse. The master then transfers an
8-bit byte address to the UFM, which acknowledges the reception of the address. The
master transfers the 8-bit data to be written to the UFM. Once the altufm_i2c logic
acknowledges the reception of the 8-bit data, the master generates a stop condition.
The internal write from the MAX II logic array to the UFM begins only after the
master generates a stop condition. While the UFM internal write cycle is in progress,
the altufm_i2c logic ignores any attempt made by the master to initiate a new transfer.
Figure 9–15 shows the Byte Write sequence.
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
