9–14
Chapter 9: Using User Flash Memory in MAX II Devices
Software Support for UFM Block
Inter-Integrated Circuit
Inter-Integrated Circuit (I
2
C) is a bidirectional two-wire interface protocol, requiring
only two bus lines; a serial data/address line (SDA), and a serial clock line (SCL).
Each device connected to the I
2
C bus is software addressable by a unique address. The
I
2
C bus is a multi-master bus where more than one integrated circuit (IC) capable of
initiating a data transfer can be connected to it, which allows masters to function as
transmitters or receivers.
The altufm_i2c megafunction features a serial, 8-bit bidirectional data transfer up to
100 Kbits per second. With the altufm_i2c megafunction, the MAX II UFM and logic
can be configured as a slave device for the I
2
C bus. The altufm megafunction’s I
2
C
interface is designed to function similar to I
2
C serial EEPROMs.
The Quartus II software supports three different memory sizes:
■
■
■
■
(128 × 8) 1 Kbits
(256 × 8) 2 Kbits
(512 × 8) 4 Kbits
(1,024 × 8) 8 Kbits
I
2
C Protocol
The following defines the characteristics of the I
2
C bus protocol:
■
Only two bus lines are required: SDA and SCL. Both SDA and SCL are
bidirectional lines which remain high when the bus is free.
Data transfer can be initiated only when the bus is free.
The data on the SDA line must be stable during the high period of the clock. The
high or low state of the data line can only change when the clock signal on the SCL
line is low.
Any transition on the SDA line while the SCL is high is one such unique case
which indicates a start or stop condition.
■
■
■
summarizes the altufm_i2c megafunction input and output interface
signals.
Table 9–5.
altufm_i2c Interface Signals
Pin
SDA
Description
Serial Data/Address Line
Function
The bidirectional SDA port is used to transmit and receive serial data from the
UFM. The output stage of the SDA port is configured as an open drain pin to
perform the wired-AND function.
The bidirectional SCL port is used to synchronize the serial data transfer to and
from the UFM. The output stage of the SCL port is configured as an open drain
pin to perform a wired-AND function.
Optional active high signal that disables the erase and write function for
read/write mode. The altufm_i2c megafunction gives you an option to protect
the entire UFM memory or only the upper half of memory.
These inputs set the UFM slave address. The A
6
, A
5
, A
4
, A
3
slave address bits
are programmable, set internally to
1010
by default.
SCL
Serial Clock Line
WP
Write Protect
A
2
,
A
1
,
A
0
Slave Address Input
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