Chapter 8: Using MAX II Devices in Multi-Voltage Systems
MultiVolt Core and I/O Operation
8–3
MultiVolt Core and I/O Operation
MAX II devices include MultiVolt core I/O operation capability, allowing the core and
I/O blocks of the device to be powered-up with separate supply voltages. The
VCCINT
pins supply power to the device core and the
VCCIO
pins supply power to
the device I/O buffers. The
VCCINT
pins can be powered-up with 1.8 V for MAX IIG
and MAX IIZ devices or 2.5/3.3 V for MAX II devices. All the
VCCIO
pins for a given
I/O bank that have MultiVolt capability should be supplied from the same voltage
level (for example, 5.0, 3.3, 2.5, 1.8, or 1.5 V). See
Figure 8–2.
Implementing a Multiple-Voltage System with a MAX II Device
1.8
V/2.5 V/3.3 V
Power Supply
V
CCINT
5.0-V
Device
V
CCIO
MAX II
Device
V
CCIO
3.3-V
Device
V
CCIO
2.5-V
Device
Notes to
:
(1) For MAX IIG and MAX IIZ devices,
VCCINT
pins will only accept a 1.8-V power supply.
(2) For MAX II devices,
VCCINT
pins will only accept a 2.5-V or 3.3-V power supply.
(3) MAX II devices can drive a 5.0-V TTL input when V
CCIO
= 3.3 V. To drive a 5.0-V CMOS, an open-drain setting with
internal I/O clamp diode and external resistor are required.
(4) MAX II devices can be 5.0-V tolerant with the use of an external resistor and the internal I/O clamp diode on EPM1270
and EPM2210 devices.
5.0-V Device Compatibility
A MAX II device can drive a 5.0-V TTL device by connecting the
V
CCIO
pins of the
MAX II device to 3.3 V. This is possible because the output high voltage (V
OH
) of a 3.3-
V interface meets the minimum high-level voltage of 2.4 V of a 5.0-V TTL device.
A MAX II device may not correctly interoperate with a 5.0-V CMOS device if the
output of the MAX II device is connected directly to the input of the 5.0-V CMOS
device. If the MAX II device‘s
V
OUT
is greater than
V
CCIO
, the PMOS pull-up transistor
still conducts if the pin is driving high, preventing an external pull-up resistor from
pulling the signal to 5.0 V. To make MAX II device outputs compatible with 5.0-V
CMOS devices, configure the output pins as open-drain pins with the I/O clamp
diode enabled, and use an external pull-up resistor. See
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