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EPM1270M100A 参数 Datasheet PDF下载

EPM1270M100A图片预览
型号: EPM1270M100A
PDF下载: 下载PDF文件 查看货源
内容描述: MAX II器件系列 [MAX II Device Family]
分类和应用:
文件页数/大小: 86 页 / 1216 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 5: DC and Switching Characteristics  
5–21  
Timing Model and Specifications  
External Timing I/O Delay Adders  
The I/O delay timing parameters for I/O standard input and output adders, and  
input delays are specified by speed grade independent of device density.  
Table 5–27 through Table 5–28 show the adder delays associated with I/O pins for all  
packages. The delay numbers for –3, –4, and –5 speed grades shown in Table 5–27  
through Table 5–30 are based on an EPM1270 device target, while –6 and –7 speed  
grade values are based on an EPM570Z device target. If an I/O standard other than  
3.3-V LVTTL is selected, add the input delay adder to the external tSU timing  
parameters shown in Table 5–23 through Table 5–26. If an I/O standard other than  
3.3-V LVTTL with 16 mA drive strength and fast slew rate is selected, add the output  
delay adder to the external tCO and tPD shown in Table 5–23 through Table 5–26.  
Table 5–27. External Timing Input Delay Adders  
–3 Speed  
Grade  
–4 Speed  
Grade  
–5 Speed  
Grade  
–6 Speed  
Grade  
–7 Speed  
Grade  
Standard  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max Unit  
3.3-V LVTTL Without Schmitt  
Trigger  
0
0
0
0
0
ps  
With  
334  
434  
535  
387  
434  
ps  
Schmitt Trigger  
3.3-V  
LVCMOS  
Without Schmitt  
Trigger  
0
0
0
0
0
ps  
ps  
With  
334  
434  
535  
387  
434  
Schmitt Trigger  
2.5-V LVTTL  
Without Schmitt  
Trigger  
23  
339  
291  
681  
0
30  
441  
378  
885  
0
37  
543  
466  
1,090  
0
42  
429  
378  
681  
0
43  
476  
373  
622  
0
ps  
ps  
ps  
ps  
ps  
With Schmitt  
Trigger  
1.8-V LVTTL  
1.5-V LVTTL  
3.3-V PCI  
Without Schmitt  
Trigger  
Without Schmitt  
Trigger  
Without Schmitt  
Trigger  
Table 5–28. MAX II IOE Programmable Delays  
–3 Speed  
Grade  
–4 Speed  
Grade  
–5 Speed  
Grade  
–6 Speed  
Grade  
–7 Speed  
Grade  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Input Delay from Pin to Internal  
Cells = 1  
1,225  
1,592  
1,960  
1,858  
2,171  
ps  
Input Delay from Pin to Internal  
Cells = 0  
89  
115  
142  
569  
609  
ps  
© Novermber 2008 Altera Corporation  
MAX II Device Handbook