Chapter 5: DC and Switching Characteristics
5–11
Timing Model and Specifications
f
For more explanations and descriptions about each internal timing microparameters
symbol, refer to the Understanding Timing in MAX II Devices chapter in the MAX II
Device Handbook.
Table 5–15. LE Internal Timing Microparameters
–3 Speed
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Unit
tLUT
LE combinational LUT
delay
—
571
—
742
—
914
—
1,215
—
2,247 ps
tCOMB
tCLR
tPRE
tSU
Combinational path delay
LE register clear delay
LE register preset delay
—
238
238
208
147
—
—
309
309
271
192
—
—
381
381
333
236
—
—
401
401
260
243
—
—
541
541
319
305
—
ps
ps
ps
ps
—
—
—
—
—
LE register setup time
before clock
—
—
—
—
—
tH
LE register hold time after
clock
0
—
235
—
0
—
305
—
0
—
376
—
0
—
380
—
0
—
489
—
ps
ps
ps
tCO
tCLKHL
tC
LE register clock-to-output
delay
—
—
—
—
—
Minimum clock high or low 166
time
216
—
266
—
253
—
335
—
Register control delay
—
857
1,114
1,372
1,356
1,722 ps
Table 5–16. IOE Internal Timing Microparameters (Part 1 of 2)
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Symbol
Parameter
Min Max Min Max
Min Max Min Max Min Max Unit
tFASTIO
Data output delay from
adjacent LE to I/O block
—
—
—
159
—
—
—
207
—
—
—
254
—
—
—
170
—
—
—
348
ps
tIN
I/O input pad and buffer
delay
708
920
1,132
2,430
907
970
ps
tGLOB (1) I/O input pad and buffer
delay used as global signal
pin
1,519
1,974
2,261
2,670 ps
tIOE
Internally generated output
enable delay
—
354
—
374
—
460
—
530
—
966
410
ps
ps
tDL
Input routing delay
—
—
224
—
—
291
—
—
358
—
—
318
—
—
tOD (2)
Output delay buffer and pad
delay
1,064
1,383
1,702
1,319
1,526 ps
© Novermber 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
