5–10
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–13. MAX II Device Timing Model Status
Device
EPM1270
Preliminary
Final
v
—
—
EPM2210
v
Note to Table 5–13:
(1) The MAX IIZ device timing models are only available in the Quartus II software version
8.0 and later.
Performance
Table 5–14 shows the MAX II device performance for some common designs. All
performance values were obtained with the Quartus II software compilation of
megafunctions. Performance values for –3, –4, and –5 speed grades are based on an
EPM1270 device target while –6 and –7 speed grades are based on an EPM570Z device
target.
Table 5–14. MAX II Device Performance
Resources Used
Performance
–5
–3
–4
–6
–7
Resource
Used
Design Size and
Function
UFM
Speed Speed Speed Speed
Speed
Mode
LEs
16
64
11
24
5
Blocks Grade
Grade
247.5
154.8
8.0
Grade
201.1
125.8
9.3
Grade
184.1
83.2
17.4
12.5
9.0
Grade Unit
LE
16-bit counter (1)
64-bit counter (1)
16-to-1 multiplexer
32-to-1 multiplexer
16-bit XOR function
—
—
—
—
—
—
0
0
0
0
0
0
304.0
201.5
6.0
123.5 MHz
83.2
17.3
22.8
15.0
15.0
MHz
ns
7.1
9.0
11.4
8.2
ns
5.1
6.6
ns
16-bit decoder with
single address line
5
5.2
6.6
8.2
9.2
ns
UFM
512 × 16
512 × 16
512 × 8
None
SPI (2)
3
1
1
1
1
10.0
8.0
10.0
8.0
10.0
8.0
10.0
9.7
10.0
9.7
MHz
MHz
MHz
37
Parallel (3)
73
(4)
(4)
(4)
(4)
(4)
2
512 × 16
I C (3)
142
100 (5) 100 (5) 100 (5) 100 (5) 100 (5) kHz
Notes to Table 5–14:
(1) This design is a binary loadable up counter.
(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of LEs used.
(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.
(4) This design is asynchronous.
(5) The I2C megafunction is verified in hardware up to 100-kHz serial clock line (SCL) rate.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device
density. Table 5–15 through Table 5–22 describe the MAX II device internal timing
microparameters for logic elements (LEs), input/output elements (IOEs), UFM
structures, and MultiTrack interconnects. The timing values for –3, –4, and –5 speed
grades shown in Table 5–15 through Table 5–22 are based on an EPM1270 device
target, while –6 and –7 speed grade values are based on an EPM570Z device target.
MAX II Device Handbook
© Novermber 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
