欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM1270GM100A 参数 Datasheet PDF下载

EPM1270GM100A图片预览
型号: EPM1270GM100A
PDF下载: 下载PDF文件 查看货源
内容描述: MAX II器件系列 [MAX II Device Family]
分类和应用:
文件页数/大小: 86 页 / 1216 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EPM1270GM100A的Datasheet PDF文件第32页浏览型号EPM1270GM100A的Datasheet PDF文件第33页浏览型号EPM1270GM100A的Datasheet PDF文件第34页浏览型号EPM1270GM100A的Datasheet PDF文件第35页浏览型号EPM1270GM100A的Datasheet PDF文件第37页浏览型号EPM1270GM100A的Datasheet PDF文件第38页浏览型号EPM1270GM100A的Datasheet PDF文件第39页浏览型号EPM1270GM100A的Datasheet PDF文件第40页  
2–28  
Chapter 2: MAX II Architecture  
I/O Structure  
Figure 2–23. MAX II I/O Banks for EPM1270 and EPM2210 (Note 1), (2)  
I/O Bank 2  
Also Supports  
the 3.3-V PCI  
I/O Standard  
All I/O Banks Support  
3.3-V LVTTL/LVCMOS  
2.5-V LVTTL/LVCMOS  
1.8-V LVTTL/LVCMOS  
1.5-V LVCMOS  
I/O Bank 1  
I/O Bank 3  
I/O Bank 4  
Notes to Figure 2–23:  
(1) Figure 2–23 is a top view of the silicon die.  
(2) Figure 2–23 is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations.  
Each I/O bank has dedicated VCCIO pins that determine the voltage standard support  
in that bank. A single device can support 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each  
individual bank can support a different standard. Each I/O bank can support  
multiple standards with the same VCCIO for input and output pins. For example, when  
V
CCIO is 3.3 V, Bank 3 can support LVTTL, LVCMOS, and 3.3-V PCI. VCCIO powers both  
the input and output buffers in MAX II devices.  
The JTAG pins for MAX II devices are dedicated pins that cannot be used as regular  
I/O pins. The pins TMS, TDI, TDO, and TCKsupport all the I/O standards shown in  
Table 2–4 on page 2–27 except for PCI. These pins reside in Bank 1 for all MAX II  
devices and their I/O standard support is controlled by the VCCIO setting for Bank 1.  
PCI Compliance  
The MAX II EPM1270 and EPM2210 devices are compliant with PCI applications as  
well as all 3.3-V electrical specifications in the PCI Local Bus Specification Revision 2.2.  
These devices are also large enough to support PCI intellectual property (IP) cores.  
Table 2–5 shows the MAX II device speed grades that meet the PCI timing  
specifications.  
MAX II Device Handbook  
© October 2008 Altera Corporation  
 复制成功!