5–18
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
shows the external I/O timing parameters for EPM240 devices.
Table 5–23.
EPM240 Global Clock External I/O Timing Parameters
–3 Speed
Grade
Symbol
t
PD1
Parameter
Worst case
pin-to-pin
delay through
1 look-up
table (LUT)
Best case pin-
to-pin delay
through
1 LUT
Global clock
setup time
Global clock
hold time
Global clock
to output
delay
Global clock
high time
Global clock
low time
Minimum
global clock
period for
16-bit counter
Maximum
global clock
frequency for
16-bit counter
Condition
10 pF
Min
—
Max
4.7
–4 Speed
Grade
Min
—
Max
6.1
–5 Speed
Grade
Min
—
Max
7.5
–6 Speed
Grade
Min
—
Max
7.9
–7 Speed
Grade
Min
—
Max
12.0
Unit
ns
t
PD2
10 pF
—
3.7
—
4.8
—
5.9
—
5.8
—
7.8
ns
t
SU
t
H
t
CO
—
—
10 pF
1.7
0.0
2.0
—
—
4.3
2.2
0.0
2.0
—
—
5.6
2.7
0.0
2.0
—
—
6.9
2.8
0
2.0
—
—
7.7
4.7
0
2.0
—
—
10.5
ns
ns
ns
t
CH
t
CL
t
CNT
—
—
—
166
166
3.3
—
—
—
216
216
4.0
—
—
—
266
266
5.0
—
—
—
253
253
5.4
—
—
—
335
335
8.1
—
—
—
ps
ps
ns
f
CNT
—
—
304.0
—
247.5
—
201.1
—
184.1
—
123.5
MHz
Note to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
ALTERA [ ALTERA CORPORATION ]
