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EPM1270GF100A 参数 Datasheet PDF下载

EPM1270GF100A图片预览
型号: EPM1270GF100A
PDF下载: 下载PDF文件 查看货源
内容描述: MAX II器件系列 [MAX II Device Family]
分类和应用:
文件页数/大小: 86 页 / 1216 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–14  
Chapter 5: DC and Switching Characteristics  
Timing Model and Specifications  
Table 5–21. UFM Block Internal Timing Microparameters (Part 1 of 2)  
–3 Speed  
Grade  
–4 Speed  
Grade  
–5 Speed  
Grade  
–6 Speed  
Grade  
–7 Speed  
Grade  
Symbol  
tACLK  
Parameter  
Min Max Min Max Min Max Min Max Min Max Unit  
Address register clock period  
100  
20  
100  
20  
100  
20  
100  
20  
100  
20  
ns  
ns  
tASU  
Address register shift signal setup  
to address register clock  
tAH  
Address register shift signal hold to  
address register clock  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
ns  
ns  
ns  
tADS  
tADH  
Address register data in setup to  
address register clock  
Address register data in hold from  
address register clock  
tDCLK  
tDSS  
Data register clock period  
100  
60  
100  
60  
100  
60  
100  
60  
100  
60  
ns  
ns  
Data register shift signal setup to  
data register clock  
tDSH  
tDDS  
tDDH  
tDP  
Data register shift signal hold from  
data register clock  
20  
20  
20  
0
20  
20  
20  
0
20  
20  
20  
0
20  
20  
20  
0
20  
20  
20  
0
ns  
ns  
ns  
ns  
Data register data in setup to data  
register clock  
Data register data in hold from data  
register clock  
Program signal to data clock hold  
time  
tPB  
Maximum delay between program  
rising edge to UFM busy signal  
rising edge  
960  
960  
960  
960  
960 ns  
tBP  
Minimum delay allowed from UFM  
busy signal going low to program  
signal going low  
20  
20  
20  
20  
20  
ns  
tPPMX  
tAE  
Maximum length of busy pulse  
during a program  
0
100  
0
100  
0
100  
0
100  
0
100 µs  
ns  
960 ns  
Minimum erase signal to address  
clock hold time  
tEB  
Maximum delay between the erase  
rising edge to the UFM busy signal  
rising edge  
960  
960  
960  
960  
tBE  
Minimum delay allowed from the  
UFM busy signal going low to erase  
signal going low  
20  
20  
20  
20  
20  
ns  
tEPMX  
tDCO  
Maximum length of busy pulse  
during an erase  
500  
5
500  
5
500  
5
500  
5
500 ms  
ns  
Delay from data register clock to  
data register output  
5
MAX II Device Handbook  
© Novermber 2008 Altera Corporation