EPM1270GF100A 参数 Datasheet PDF下载

型号：	EPM1270GF100A
PDF下载：	下载PDF文件查看货源
内容描述：	MAX II器件系列 [MAX II Device Family]
分类和应用：
文件页数/大小：	86 页 / 1216 K
品牌：	ALTERA [ ALTERA CORPORATION ]

5–14

Chapter 5: DC and Switching Characteristics

Timing Model and Specifications

Table 5–21. UFM Block Internal Timing Microparameters (Part 1 of 2)

–3 Speed

Grade

–4 Speed

Grade

–5 Speed

Grade

–6 Speed

Grade

–7 Speed

Grade

Symbol

t_ACLK

Parameter

Min Max Min Max Min Max Min Max Min Max Unit

Address register clock period

100

—

100

—

100

—

100

—

100

—

t_ASU

Address register shift signal setup

to address register clock

t_AH

Address register shift signal hold to

address register clock

—

t_ADS

t_ADH

Address register data in setup to

address register clock

Address register data in hold from

address register clock

t_DCLK

t_DSS

Data register clock period

100

—

100

—

100

—

100

—

100

—

Data register shift signal setup to

data register clock

t_DSH

t_DDS

t_DDH

t_DP

Data register shift signal hold from

data register clock

—

Data register data in setup to data

Data register data in hold from data

—

Program signal to data clock hold

time

—

t_PB

Maximum delay between program

rising edge to UFM busy signal

rising edge

—

960

—

960

—

960

—

960

—

960 ns

t_BP

Minimum delay allowed from UFM

busy signal going low to program

signal going low

—

t_PPMX

t_AE

Maximum length of busy pulse

during a program

—

100

—

100

—

100

—

100

—

100 µs

960 ns

Minimum erase signal to address

clock hold time

—

t_EB

Maximum delay between the erase

rising edge to the UFM busy signal

rising edge

—

960

—

960

—

960

—

960

—

t_BE

Minimum delay allowed from the

UFM busy signal going low to erase

signal going low

—

t_EPMX

t_DCO

Maximum length of busy pulse

during an erase

—

500

—

500

—

500

—

500

—

500 ms

Delay from data register clock to

data register output

MAX II Device Handbook

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